Tadahiko Sugibayashi

According to our database, Tadahiko Sugibayashi authored at least 37 papers between 1993 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation.

Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Naoki Banno, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

IEICE Trans. Electron., October, 2022

Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation.

Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

IEEE J. Solid State Circuits, 2022

2020

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.

Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution.

Koichiro Okamoto, Ryusuke Nebashi, Naoki Banno, Xu Bai, Hideaki Numata, Noriyuki Iguchi, Makoto Miyamura, Hiromitsu Hada, Kazunori Funahashi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS.

Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2018

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.

Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto

IEEE Trans. Very Large Scale Integr. Syst., 2018

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.

Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto

IEEE Embed. Syst. Lett., 2018

2017

NanoBridge-Based FPGA in High-Temperature Environments.

Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji, Ayuka Morioka, Ryusuke Nebashi, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi, Yuya Nagamatsu, Soichi Ookubo, Takuma Shirai, Fumihito Sugai, Masayuki Inaba

IEEE Micro, 2017

2016

Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory.

Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

J. Multiple Valued Log. Soft Comput., 2016

A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond.

Yukihide Tsuji, Xu Bai, Ayuka Morioka, Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE J. Solid State Circuits, 2015

2014

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.

Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.

Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.

Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Soft-Delay-Error Evaluation in Content-Addressable Memory.

Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.

Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi

Inf. Media Technol., 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI.

Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors.

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.

Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.

Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai

IEICE Trans. Electron., 2009

A 90nm 12ns 32Mb 2T1MTJ MRAM.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs.

Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

A 16-Mb Toggle MRAM With Burst Modes.

Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara

IEEE J. Solid State Circuits, 2007

MRAM Cell Technology for Over 500-MHz SoC.

Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara

IEEE J. Solid State Circuits, 2007

MRAM Applications Using Unlimited Write Endurance.

Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai

IEICE Trans. Electron., 2007

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.

Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara

IEICE Trans. Electron., 2007

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

Resistance ratio read (R³) architecture for a burst operated 1.5V MRAM macro.

Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2000

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.

Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani

IEEE J. Solid State Circuits, 2000

1999

Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM.

Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu, Tadahiko Sugibayashi

IEEE J. Solid State Circuits, 1999

1995

A 1-Gb DRAM for file applications.

Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa

IEEE J. Solid State Circuits, November, 1995

1993

A 30-ns 256-Mb DRAM with a multidivided array structure.

Tadahiko Sugibayashi, Toshio Takeshima, Isao Naritake, Tatsuya Matano, Hiroshi Takada, Yoshiharu Aimoto, Koichiro Furuta, Mamoru Fujita, Takanori Saeki, Hiroshi Sugawara, Tatsunori Murotani, Naoki Kasai, Kentaro Shibahara, Ken Nakajima, Hiromitsu Hada, Takehiko Hamada, Naoaki Aizaki, Takemitsu Kunio, Eiichiro Kakehashi, Katsuhiro Masumori, Takaho Tanigawa

IEEE J. Solid State Circuits, November, 1993