Huawei Li

According to our database1, Huawei Li authored at least 176 papers between 1998 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection.
CoRR, 2019

Scan Chain Based Attacks and Countermeasures: A Survey.
IEEE Access, 2019

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Secure and Low-overhead Active IC Metering Scheme.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Exploring emerging CNFET for efficient last level cache design.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

P3M: a PIM-based neural network model protection scheme for deep learning accelerator.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection.
IEEE Trans. VLSI Syst., 2018

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency.
J. Comput. Sci. Technol., 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Innovative practices on challenges, opportunities, and solutions to hardware security.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Lightweight Timing Channel Protection for Shared DRAM Controller.
Proceedings of the IEEE International Test Conference, 2018

FCN-engine: accelerating deconvolutional layers in classic CNN processors.
Proceedings of the International Conference on Computer-Aided Design, 2018

A retrospective evaluation of energy-efficient object detection solutions on embedded devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Hardware Trojan Detection Based on Signal Correlation.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A New Scheme to Extract PUF Information by Scan Chain.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

XORiM: A case of in-memory bit-comparator implementation and its performance implications.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A low-overhead PUF based on parallel scan design.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Bias PUF based Secure Scan Chain Design.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.
IEEE Trans. VLSI Syst., 2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Why current secure scan designs fail and how to fix them?
Integration, 2017

Innovative practices session 10C formal verification practices in industry.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Flip-flop clustering based trace signal selection for post-silicon debug.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Software-based online self-testing of network-on-chip using bounded model checking.
Proceedings of the IEEE International Test Conference, 2017

A regularized on-line sequential extreme learning machine with forgetting property for fast dynamic hysteresis modeling.
Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR.
Proceedings of the 54th Annual Design Automation Conference, 2017

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.
Proceedings of the Computing Frontiers Conference, 2017

How to Secure Scan Design Against Scan-Based Side-Channel Attacks?
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Test and Reliability of Emerging Non-volatile Memories.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

A New Active IC Metering Technique Based on Locking Scan Cells.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. VLSI Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.
IEEE Trans. VLSI Syst., 2016

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands.
ACM Trans. Design Autom. Electr. Syst., 2016

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition.
IEEE Trans. Computers, 2016

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs.
Integration, 2016

Path constraint solving based test generation for observability-enhanced branch coverage.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.
Proceedings of the 2016 IEEE International Test Conference, 2016

A new countermeasure against scan-based side-channel attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

An ultra-low overhead LUT-based PUF for FPGA.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Task Scheduling in Cloud Computing Based on Cross Entropy Method.
Proceedings of the Geo-Spatial Knowledge and Intelligence, 2016

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.
Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Data Remapping for Static NUCA in Degradable Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.
IEEE Trans. VLSI Syst., 2015

Survey of WDM network reconfiguration: topology migrations and their impact on service disruptions.
Telecommunication Systems, 2015

An on-chip frequency programmable test clock generation and application method for small delay defect detection.
Integration, 2015

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island.
Proceedings of the VLSI Design, Automation and Test, 2015

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Temperature-aware software-based self-testing for delay faults.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Retraining-based timing error mitigation for hardware neural networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

TURO: A lightweight turn-guided routing scheme for 3D NoCs.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Lightweight Timing Channel Protection for Shared Memory Controllers.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. VLSI Syst., 2014

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.
IEEE Trans. VLSI Syst., 2014

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications.
IEEE Trans. VLSI Syst., 2014

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach.
TACO, 2014

Reinventing Memory System Design for Many-Accelerator Architecture.
J. Comput. Sci. Technol., 2014

A novel abstraction-guided simulation approach using posterior probabilities for verification.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Functional test generation guided by steady-state probabilities of abstract design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power DRAM refresh control scheme for 3D memory cube.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

An On-Line Timing Error Detection Method for Silicon Debug.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.
IEEE Trans. VLSI Syst., 2013

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.
IEEE Trans. VLSI Syst., 2013

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model.
IEEE Trans. VLSI Syst., 2013

RSAK: Random stream attack for phase change memory in video applications.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Surface tension-induced high aspect-ratio PDMS micropillars with concave and convex lens tips.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

Low-cost rapid prototyping of flexible plastic paper based microfluidic devices.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

Integrated lenses in polystyrene microfluidic devices.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Path Constraint Solving Based Test Generation for Hard-to-Reach States.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume.
IEEE Trans. VLSI Syst., 2012

A High-Precision On-Chip Path Delay Measurement Architecture.
IEEE Trans. VLSI Syst., 2012

Testable Path Selection and Grouping for Faster Than At-Speed Testing.
IEEE Trans. VLSI Syst., 2012

Statistical SDFC: A metric for evaluating test quality of small delay faults.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.
IEEE Trans. VLSI Syst., 2011

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects.
IEEE Trans. VLSI Syst., 2011

Statistical lifetime reliability optimization considering joint effect of process variation and aging.
Integration, 2011

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.
IEICE Transactions, 2011

A unified test architecture for on-line and off-line delay fault detections.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

An abacus turn model for time/space-efficient reconfigurable routing.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
Proceedings of the Design, Automation and Test in Europe, 2011

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Testable Critical Path Selection Considering Process Variation.
IEICE Transactions, 2010

Fast path selection for testing of small delay defects considering path correlations.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
Proceedings of the 2011 IEEE International Test Conference, 2010

On generation of a universal path candidate set containing testable long paths.
Proceedings of the 2011 IEEE International Test Conference, 2010

An on-chip clock generation scheme for faster-than-at-speed delay testing.
Proceedings of the Design, Automation and Test in Europe, 2010

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

The Application of the Optimum of MDOD in Structure Design of Double Reels for Wrapped Hoist.
Proceedings of the International Conference on Computational Aspects of Social Networks, 2010

Software-Based Self-Testing of Processors Using Expanded Instructions.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Graph partition based path selection for testing of small delay defects.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.
IEEE Trans. VLSI Syst., 2009

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip.
J. Comput. Sci. Technol., 2009

Automatic Selection of Internal Observation Signals for Design Verification.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact of Hazards on Pattern Selection for Small Delay Defects.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Small Delay Fault Simulation for Sequential Circuits.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Low Overhead On-Chip Path Delay Measurement Circuit.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.
J. Comput. Sci. Technol., 2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Multiple Coupling Effects Oriented Path Delay Test Generation.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

Static Crosstalk Noise Analysis with Transition Map.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Case Study on At-Speed Testing for a Gigahertz Microprocessor.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Scan-Based Delay Test Method for Reduction of Overtesting.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robust test generation for power supply noise induced path delay faults.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst., 2007

The design-for-testability features of a general purpose microprocessor.
Proceedings of the 2007 IEEE International Test Conference, 2007

Bug analysis and corresponding error models in real designs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Routing Algorithm for Random Error Tolerance in Network-on-Chip.
Proceedings of the Human-Computer Interaction. HCI Applications and Services, 2007

2006
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.
IEEE Trans. Instrumentation and Measurement, 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions, 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences, 2006

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fast Packet Classification using Group Bit Vector.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Impact of Load Characteristics and Low-Voltage Load Shedding Schedule on Dynamic Voltage Stability.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Chaos and Ferroresonance.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
An innovative free memory design for network processors in home network gateway.
IEEE Trans. Consumer Electronics, 2005

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions, 2005

Selection of Crosstalk-Induced Faults in Enhanced Delay Test.
J. Electronic Testing, 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Using MUXs Network to Hide Bunches of Scan Chains.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Non-robust Test Generation for Crosstalk-Induced Delay Faults.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design of an efficient memory subsystem for network processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Pair Balance-Based Test Scheduling for SOCs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A Novel RT-Level Behavioral Description Based ATPG Method.
J. Comput. Sci. Technol., 2003

Delay Test Pattern Generation Considering Crosstalk-Induced Effects.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Clustering of behavioral phases in FSMs and its applications to VLSI test.
Science in China Series F: Information Sciences, 2002

Test Power Optimization Techniques for CMOS Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Reducing Power Dissipation during At-Speed Test Application.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An RT-Level ATPG Based on Clustering of Circuit States.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Reduction of Number of Paths to be Tested in Delay Testing.
J. Electronic Testing, 2000

1998
Delay Testing with Double Observations.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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