Steven J. E. Wilton

According to our database1, Steven J. E. Wilton authored at least 147 papers between 1993 and 2019.

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2019
Layout-Aware Embedding for Quantum Annealing Processors.
Proceedings of the High Performance Computing - 34th International Conference, 2019

An Overlay for Rapid FPGA Debug of Machine Learning Applications.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Towards In-Circuit Tuning of Deep Learning Designs.
Proceedings of the International Conference on Computer-Aided Design, 2019

On-chip FPGA Debug Instrumentation for Machine Learning Applications.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Introduction to the Special Section on Deep Learning in FPGAs.
TRETS, 2018

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug.
ACM Trans. Design Autom. Electr. Syst., 2018

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks.
CoRR, 2018

Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques.
Proceedings of the International Conference on Field-Programmable Technology, 2018

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Architecture Exploration for HLS-Oriented FPGA Debug Overlays.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Rapid circuit-specific inlining tuning for FPGA high-level synthesis.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating.
IEEE Trans. VLSI Syst., 2016

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug.
SIGARCH Computer Architecture News, 2016

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges.
CoRR, 2016

RAW Introduction and Committees.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Quantifying observability for in-system debug of high-level synthesis circuits.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Systems-on-Chip on FPGAs.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Allowing Software Developers to Debug HLS Hardware.
CoRR, 2015

RAW Introduction and Committees.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

An adaptive virtual overlay for fast trigger insertion for FPGA debug.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Hierarchical Dynamic Power-Gating in FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Incremental Trace-Buffer Insertion for FPGA Debug.
IEEE Trans. VLSI Syst., 2014

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network.
ACM Trans. Design Autom. Electr. Syst., 2014

Power Aware Architecture Exploration for Field Programmable Gate Arrays.
J. Low Power Electronics, 2014

A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices.
J. Low Power Electronics, 2014

Effective FPGA debug for high-level synthesis generated circuits.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Incremental distributed trigger insertion for efficient FPGA debug.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Scalable Signal Selection for Post-Silicon Debug.
IEEE Trans. VLSI Syst., 2013

Towards development of an analytical model relating FPGA architecture parameters to routability.
TRETS, 2013

Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.
IEEE Trans. Computers, 2013

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics.
IEEE Design & Test, 2013

Maximum flow algorithms for maximum observability during FPGA debug.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Optimizing Floating Point Units in Hybrid FPGAs.
IEEE Trans. VLSI Syst., 2012

Formal-Analysis-Based Trace Computation for Post-Silicon Debug.
IEEE Trans. VLSI Syst., 2012

Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation.
ACM Trans. Embedded Comput. Syst., 2012

Multi-objective voltage island floorplanning using sequence pair representation.
Sustain. Comput. Informatics Syst., 2012

Emulation in post-silicon validation: It's not just for functionality anymore.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Rapid RTL-based signal ranking for FPGA prototyping.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

VersaPower: Power estimation for diverse FPGA architectures.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

An FPGA with power-gated switch blocks.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Limitations of incremental signal-tracing for FPGA debug.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Advances in 3D design and optimization.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
An Analytical Model Relating FPGA Architecture to Logic Density and Depth.
IEEE Trans. VLSI Syst., 2011

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs).
IEEE Trans. VLSI Syst., 2011

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

On evaluating signal selection algorithms for post-silicon debug.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Sequence pair based voltage island floorplanning.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Accelerated FPGA architecture design: Capabilities and limitations of analytical models.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Speculative Debug Insertion for FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An analytical model relating FPGA architecture parameters to routability.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Towards scalable FPGA CAD through architecture.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Accelerating trace computation in post-silicon debug.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An FPGA architecture supporting dynamically controlled power gating.
Proceedings of the International Conference on Field-Programmable Technology, 2010

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Towards Analytical Methods for FPGA Architecture Investigation.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces.
IEEE Trans. VLSI Syst., 2009

Floating-Point FPGA: Architecture and Modeling.
IEEE Trans. VLSI Syst., 2009

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms.
TRETS, 2009

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

A detailed delay path model for FPGAs.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Modeling post-techmapping and post-clustering FPGA circuit depth.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Improving the memory footprint and runtime scalability of FPGA CAD algorithms.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

An analytical model relating FPGA architecture and place and route runtime.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Charge-borrowing decap: A novel circuit for removal of local supply noise violations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Field-Programmable Gate Array Architectures.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Practical Asynchronous Interconnect Network Design.
IEEE Trans. VLSI Syst., 2008

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.
IEEE Trans. VLSI Syst., 2008

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.
TRETS, 2008

On the trade-off between power and flexibility of FPGA clock networks.
TRETS, 2008

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.
Int. J. Reconfig. Comp., 2008

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays.
Int. J. Reconfig. Comp., 2008

BackSpace: Moving Towards Reality.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Optimizing coarse-grained units in floating point hybrid FPGA.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A system-level stochastic circuit generator for FPGA architecture evaluation.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

An analytical model describing the relationships between logic architecture and FPGA density.
Proceedings of the FPL 2008, 2008

Rapid estimation of power consumption for hybrid FPGAs.
Proceedings of the FPL 2008, 2008

BackSpace: Formal Analysis for Post-Silicon Debug.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

Session 14 - Advanced SoCs - techniques and applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Memory Footprint Reduction for FPGA Routing Algorithms.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Embedded Programmable Logic Core Enhancements for System Bus Interfaces.
Proceedings of the FPL 2007, 2007

Clock-Aware Placement for FPGAs.
Proceedings of the FPL 2007, 2007

Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.
Proceedings of the FPL 2007, 2007

A synthesizable datapath-oriented embedded FPGA fabric.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

GlitchLess: an active glitch minimization technique for FPGAs.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006
Product-Term-Based Synthesizable Embedded Programmable Logic Cores.
IEEE Trans. VLSI Syst., 2006

System-on-Chip: Reuse and Integration.
Proceedings of the IEEE, 2006

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Architecture and CAD for FPGA Clock Networks.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Activity Estimation for Field-Programmable Gate Arrays.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA clock network architecture: flexibility vs. area and power.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
A novel FPGA architecture supporting wide, shallow memories.
IEEE Trans. VLSI Syst., 2005

Routing architecture optimizations for high-density embedded programmable IP cores.
IEEE Trans. VLSI Syst., 2005

A detailed power model for field-programmable gate arrays.
ACM Trans. Design Autom. Electr. Syst., 2005

On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays.
J. Low Power Electronics, 2005

Challenges and opportunities for low power FPGAs in nanometer technologies.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Concentrator access networks for programmable logic cores on SoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Post-Silicon Debug Using Programmable Logic Cores.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Dynamic Voltage Scaling for Commercial FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Advances in programmable logic.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Placement and routing for non-rectangular embedded programmable logic cores in SoC design.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.
Proceedings of the Field Programmable Logic and Application, 2004

Sequential synthesizable embedded programmable logic cores for system-on-chip.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
On the Interaction Between Power-Aware FPGA CAD Algorithms.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Placement and routing for FPGA architectures supporting wide shallow memories.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Architectures and algorithms for synthesizable embedded programmable logic cores.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Implementing logic in FPGA memory arrays: heterogeneous memory architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Sensitivity of FPGA power evaluation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

A Flexible Power Model for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Structural analysis and generation of synthetic digital circuits with memory.
IEEE Trans. VLSI Syst., 2001

Macrocell Architectures for Product Term Embedded Memory Arrays.
Proceedings of the Field-Programmable Logic and Applications, 2001

A crosstalk-aware timing-driven router for FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Detailed routing architectures for embedded programmable logic IP cores.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000
Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

FPGA Implementation of a Prototype WDM On-Line Scheduler.
Proceedings of the Field-Programmable Logic and Applications, 2000

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999
The memory/logic interface in FPGAs with large embedded memory arrays.
IEEE Trans. VLSI Syst., 1999

A New Switch Block for Segmented FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1995
Architecture of Centralized Field-Configurable Memory.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
Tradeoffs in Two-Level On-Chip Caching.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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