Nilanjan Mukherjee

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Test point insertion in hybrid test compression/LBIST architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Minimal area test points for deterministic patterns.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

On Test Points Enhancing Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Low-Power Programmable PRPG With Test Compression Capabilities.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Isometric Test Data Compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Innovative practices session 11C: Advanced scan methodologies [3 presentations].

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Embedded deterministic test points for compact cell-aware tests.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Design for low test pattern counts.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Innovative practices session 1C: Existing/emerging low power techniques.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Isometric test compression with low toggling activity.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

On Using Implied Values in EDT-based Test Compression.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Test Time Reduction in EDT Bandwidth Management for SoC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Deploying Scan Chains for Data Storage in Test Compression Environment.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

New test compression scheme based on low power BIST.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

EDT Bandwidth Management in SoC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low power programmable PRPG with enhanced fault coverage gradient.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

BIST-Based Fault Diagnosis for Read-Only Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.

[BibT_eX]

[DOI]

Przemyslaw Szczerbicki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Ring Generator: An Ultimate Linear Feedback Shift Register.

[BibT_eX]

[DOI]

Computer, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced ATE Interface for High Test Data Compression.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Fault Diagnosis in Memory BIST Environment with Non-march Tests.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power Aware Embedded Test.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Compaction Utilizing Inter and Intra-Correlation of Unknown States.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Low capture power at-speed test in EDT environment.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Dynamic channel allocation for higher EDT compression in SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Low power compression of incompatible test cubes.

[BibT_eX]

[DOI]

Przemyslaw Szczerbicki

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Highly X-Tolerant Selective Compaction of Test Responses.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Defect Aware to Power Conscious Tests - The New DFT Landscape.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

High-Speed On-Chip Event Counters for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Fault diagnosis for embedded read-only memories.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Compression based on deterministic vector clustering of incompatible test cubes.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

High Test Quality in Low Pin Count Applications.

[BibT_eX]

[DOI]

Jayant D'Souza

Subramanian Mahadevan

Proceedings of the 2008 IEEE International Test Conference, 2008

Targeting "Zero DPPM" - Can we ever get there?

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

A RTL Testability Analyzer Based on Logical Virtual Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

High Performance Dense Ring Generators.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

X-Press Compactor for 1000x Reduction of Test Data.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Full-speed field programmable memory BIST supporting multi-level looping.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Chasing subtle embedded RAM defects for nanometer technologies.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Full-speed field-programmable memory BIST architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Improving Test Quality Using Test Data Compression.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Achieving High Test Quality with Reduced Pin Count Testing.

[BibT_eX]

[DOI]

Jay Jahangiri

Wu-Tung Cheng

Subramanian Mahadevan

Ron Press

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Embedded deterministic test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Planar High Performance Ring Generators.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Test for Low Cost Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Cost of Test - Taking Control.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Embedded Deterministic Test for Low-Cost Manufacturing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Synthesis of Scan Chains for Netlist Descriptions at RT-Level.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Testing Schemes for FIR Filter Structures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

On RTL scan design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999

Built in self test: a complete test solution for telecommunication systems.

[BibT_eX]

[DOI]

Tapan J. Chakraborty

Ramesh Karri

IEEE Commun. Mag., 1999

1998

A BIST scheme for the detection of path-delay faults.

[BibT_eX]

[DOI]

Tapan J. Chakraborty

Sudipta Bhawmik

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Design of Testable Multipliers for Fixed-Width Data Paths.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Parameterizable Testing Scheme for FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995

Arithmetic built-in self test for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On testable multipliers for fixed-width data path architectures.

[BibT_eX]

[DOI]