Evangeline F. Y. Young

According to our database, Evangeline F. Y. Young authored at least 186 papers between 1997 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2024

Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023).

Evangeline F. Y. Young

IEEE Des. Test, 2024

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.

Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou

CoRR, 2024

Accelerating Physical Design from 1 to N.

Evangeline F. Y. Young

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning.

Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

GAMER: GPU-Accelerated Maze Routing.

Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning.

Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

GPU Acceleration in Physical Synthesis.

Evangeline F. Y. Young

Proceedings of the 2023 International Symposium on Physical Design, 2023

Security Closure of IC Layouts Against Hardware Trojans.

Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young

Proceedings of the 2023 International Symposium on Physical Design, 2023

FastPass: Fast Pin Access Analysis with Incremental SAT Solving.

Fangzhou Wang, Jinwei Liu, Evangeline F. Y. Young

Proceedings of the 2023 International Symposium on Physical Design, 2023

SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems.

Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems.

Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Rethinking AIG Resynthesis in Parallel.

Tianji Liu, Evangeline F. Y. Young

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

EDGE: Efficient DAG-based Global Routing Engine.

Jinwei Liu, Evangeline F. Y. Young

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems.

Dan Zheng, Evangeline F. Y. Young

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Pin-Accessible Legalization for Mixed-Cell-Height Circuits.

Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network.

Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization.

Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement.

Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao

Proceedings of the IEEE International Test Conference, 2022

Challenges and Approaches in VLSI Routing.

Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A2-ILT: GPU accelerated ILT with spatial attention mechanism.

Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Partition and place finite element model on wafer-scale engine.

Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Xplace: an extremely fast and extensible global placement framework.

Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

NovelRewrite: node-level parallel AIG rewriting.

Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation.

Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Building up End-to-end Mask Optimization Framework with Self-training.

Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation.

Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning.

Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment.

Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method.

Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems.

Chak-Wa Pui, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2020

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection.

Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg

ACM Trans. Design Autom. Electr. Syst., 2020

GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets.

Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration.

Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm.

Gengjie Chen, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search.

Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Layout Pattern Generation and Legalization with Generative Learning Models.

Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization.

Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing.

Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning.

Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model.

Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order.

Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham

ACM Trans. Design Autom. Electr. Syst., 2019

Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.

Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond.

Jian Kuang, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.

Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg

CoRR, 2019

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems.

Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young

Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

Session details: Patterning and Machine Learning.

Evangeline F. Y. Young

Proceedings of the 2019 International Symposium on Physical Design, 2019

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction.

Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young

Proceedings of the International Conference on Computer-Aided Design, 2019

Dim Sum: Light Clock Tree by Small Diameter Sum.

Gengjie Chen, Evangeline F. Y. Young

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.

Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FIT: Fill Insertion Considering Timing.

Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses.

Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A fast machine learning-based mask printability predictor for OPC acceleration.

Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Detailed routing by sparse grid graph and minimum-area-captured path search.

Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.

Jian Kuang, Evangeline F. Y. Young, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning.

Jian Kuang, Junjie Ye, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.

Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration.

Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning.

Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

GAN-OPC: mask optimization with lithography-guided generative adversarial nets.

Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young

Proceedings of the 55th Annual Design Automation Conference, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.

Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu

Proceedings of the 55th Annual Design Automation Conference, 2018

A two-step search engine for large scale boolean matching under NP3 equivalence.

Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Lithography hotspot detection: From shallow to deep learning.

Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Timing driven routing tree construction.

Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Fence-aware detailed-routability driven placement.

Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Bilinear Lithography Hotspot Detection.

Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm.

Gengjie Chen, Peishan Tu, Evangeline F. Y. Young

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning.

Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young

Proceedings of the 54th Annual Design Automation Conference, 2017

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.

Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Slicing Floorplan Orientation.

Evangeline F. Y. Young

Encyclopedia of Algorithms, 2016

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

IEEE Trans. Very Large Scale Integr. Syst., 2016

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology.

Evangeline F. Y. Young, Azadeh Davoodi

ACM Trans. Design Autom. Electr. Syst., 2016

An Effective Chemical Mechanical Polishing Fill Insertion Approach.

Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2016

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement.

Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2016

Placement: From Wirelength to Detailed Routability.

Wing-Kai Chow, Evangeline F. Y. Young

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Row-structure stencil planning approaches for E-beam lithography with overlapped characters.

Jian Kuang, Evangeline F. Y. Young

Integr., 2016

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization.

Hang Zhang, Bei Yu, Evangeline F. Y. Young

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.

Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incorporating cut redistribution with mask assignment to enable 1D gridded design.

Jian Kuang, Evangeline F. Y. Young, Bei Yu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Optimization for Multiple Patterning Lithography with cutting process and beyond.

Jian Kuang, Evangeline F. Y. Young

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Legalization algorithm for multiple-row height standard cell design.

Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the 53rd Annual Design Automation Conference, 2016

Simultaneous template optimization and mask assignment for DSA with multiple patterning.

Jian Kuang, Junjie Ye, Evangeline F. Y. Young

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

VLSI layout hotspot detection based on discriminative feature extraction.

Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

3D floorplan representations: Corner links and partial order.

Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Planning Massive Interconnects in 3-D Chips.

Johann Knechtel, Evangeline F. Y. Young, Jens Lienig

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Effective Chemical Mechanical Polishing Filling Approach.

Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

An effective triple patterning aware grid-based detailed routing approach.

Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A robust approach for process variation aware mask optimization.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.

Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham

Integr., 2014

A Fast Hypergraph Bipartitioning Algorithm.

Wenzan Cai, Evangeline F. Y. Young

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Cell density-driven detailed placement with displacement constraint.

Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young

Proceedings of the International Symposium on Physical Design, 2014

A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters.

Jian Kuang, Evangeline F. Y. Young

Proceedings of the International Symposium on Physical Design, 2014

Reducing pin count on cross-referencing Digital Microfluidic Biochip.

Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Overlapping-aware throughput-driven stencil planning for E-beam lithography.

Jian Kuang, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Triple patterning lithography aware optimization for standard cell based design.

Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only).

Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

General purpose cross-referencing Microfluidic Biochip with reduced pin-count.

Jackson H. C. Yeung, Evangeline F. Y. Young

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Structural planning of 3D-IC interconnects by block alignment.

Johann Knechtel, Evangeline F. Y. Young, Jens Lienig

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles.

Tao Huang, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Ripple: A Robust and Effective Routability-Driven Placer.

Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

MDiag: Mobility-assisted diagnosis for wireless sensor networks.

Junjie Xiong, Yangfan Zhou, Michael R. Lyu, Evan F. Y. Young

J. Netw. Comput. Appl., 2013

SRP: simultaneous routing and placement for congestion refinement.

Xu He, Wing-Kai Chow, Evangeline F. Y. Young

Proceedings of the International Symposium on Physical Design, 2013

An efficient layout decomposition approach for triple patterning lithography.

Jian Kuang, Evangeline F. Y. Young

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Ripple 2.0: high quality routability-driven placement via global router integration.

Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Postplacement Voltage Island Generation.

Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2012

Postgrid Clock Routing for High Performance Microprocessor Designs.

Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Construction of rectilinear Steiner minimum trees with slew constraints over obstacles.

Tao Huang, Evangeline F. Y. Young

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Crosslink insertion for variation-driven clock network construction.

Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Placement and Routing for Cross-Referencing Digital Microfluidic Biochips.

Zigang Xiao, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.

Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints.

Qiang Ma, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

MSV-Driven Floorplanning.

Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees.

Tao Huang, Liang Li, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Grid-to-ports clock routing for high performance microprocessor designs.

Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze

Proceedings of the 2011 International Symposium on Physical Design, 2011

Ripple: An effective routability-driven placer by iterative cell movement.

Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A monte-carlo floating-point unit for self-validating arithmetic.

Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An optimal algorithm for layer assignment of bus escape routing on PCBs.

Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong

Proceedings of the 48th Design Automation Conference, 2011

An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles.

Tao Huang, Evangeline F. Y. Young

Proceedings of the 48th Design Automation Conference, 2011

A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing.

Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.

Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng

ACM Trans. Design Autom. Electr. Syst., 2010

Multivoltage Floorplan Design.

Qiang Ma, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Droplet-routing-aware module placement for cross-referencing biochips.

Zigang Xiao, Evangeline F. Y. Young

Proceedings of the 2010 International Symposium on Physical Design, 2010

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.

Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng

Proceedings of the 2010 International Symposium on Physical Design, 2010

Practical placement and routing techniques for analog circuit designs.

Linfu Xiao, Evangeline F. Y. Young, Xiao-Yong He, Kong-Pang Pun

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Local clock skew minimization using blockage-aware mixed tree-mesh clock network.

Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach.

Tao Huang, Evangeline F. Y. Young

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

CrossRouter: a droplet router for cross-referencing digital microfluidic biochips.

Zigang Xiao, Evangeline F. Y. Young

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Fixed-outline thermal-aware 3D floorplanning.

Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A dual-MST approach for clock network synthesis.

Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Congestion prediction in early stages of physical design.

Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu

ACM Trans. Design Autom. Electr. Syst., 2009

Block flipping and white space distribution for wirelength minimization.

Chiu-Wing Sham, Evangeline F. Y. Young

Integr., 2009

Handling routability in floorplan design with twin binary trees.

Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu

Integr., 2009

Multi-voltage floorplan design with optimal voltage assignment.

Zaichen Qian, Evangeline F. Y. Young

Proceedings of the 2009 International Symposium on Physical Design, 2009

Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree.

Liang Li, Zaichen Qian, Evangeline F. Y. Young

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Analog placement with common centroid and 1-D symmetry constraints.

Linfu Xiao, Evangeline F. Y. Young

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Floorplan Representations.

Evangeline F. Y. Young

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Global Interconnect Planning.

Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Slicing Floorplan Orientation.

Evangeline F. Y. Young

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Optimizing wirelength and routability by searching alternative packings in floorplanning.

Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou

ACM Trans. Design Autom. Electr. Syst., 2008

Multi-bend bus driven floorplanning.

Jill H. Y. Law, Evangeline F. Y. Young

Integr., 2008

3-D floorplanning using labeled tree and dual sequences.

Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng

Proceedings of the 2008 International Symposium on Physical Design, 2008

Network flow-based power optimization under timing constraints in MSV-driven floorplanning.

Qiang Ma, Evangeline F. Y. Young

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Obstacle-avoiding rectilinear Steiner tree construction.

Liang Li, Evangeline F. Y. Young

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

TCG-based multi-bend bus driven floorplanning.

Tilen Ma, Evangeline F. Y. Young

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Area reduction by deadspace utilization on interconnect optimized floorplan.

Chiu-Wing Sham, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2007

Wire Retiming Problem With Net Topology Optimization.

Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Test scheduling for built-in self-tested embedded SRAMs with data retention faults.

Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young

IET Comput. Digit. Tech., 2007

Analog placement with common centroid constraints.

Qiang Ma, Evangeline F. Y. Young, Kong-Pang Pun

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Voltage island-driven floorplanning.

Qiang Ma, Evangeline F. Y. Young

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Analog placement with symmetry and other placement constraints.

Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Post-placement voltage island generation.

Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Block alignment in 3D floorplan using layered TCG.

Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Shuttle mask floorplanning with modified alpha-restricted grid.

Royce L. S. Ching, Evangeline F. Y. Young

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Retention-Aware Test Scheduling for BISTed Embedded SRAMs.

Qiang Xu, Baosheng Wang, F. Y. Young

Proceedings of the 11th European Test Symposium, 2006

Optimal cell flipping in placement and floorplanning.

Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu

Proceedings of the 43rd Design Automation Conference, 2006

2005

Congestion prediction in early stages.

Chiu-Wing Sham, Evangeline F. Y. Young

Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Congestion prediction in floorplanning.

Chiu-Wing Sham, Evangeline F. Y. Young

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Placement constraints in floorplan design.

Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho

IEEE Trans. Very Large Scale Integr. Syst., 2004

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.

Chris C. N. Chu, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Performance-driven register insertion in placement.

Dennis K. Y. Tong, Evangeline F. Y. Young

Proceedings of the 2004 International Symposium on Physical Design, 2004

2003

Slicing floorplan with clustering constraint.

Wing Seung Yuen, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Twin binary sequences: a nonredundant representation for general nonslicing floorplan.

Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Routability-driven floorplanner with buffer block planning.

Chiu-Wing Sham, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Temporal logic replication for dynamically reconfigurable FPGA partitioning.

Wai-Kei Mak, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Retiming with Interconnect and Gate Delay.

Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Clustering based acyclic multi-way partitioning.

Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.

Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu

Proceedings of the 2003 Design, 2003

Fast buffer planning and congestion optimization in interconnect-driven floorplanning.

Keith W. C. Wong, Evangeline F. Y. Young

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Interconnect-driven floorplanning by searching alternative packings.

Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.

Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Twin binary sequences: a non-redundant representation for general non-slicing floorplan.

Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen

Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion Estimation with Buffer Planning in Floorplan Design.

Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young

Proceedings of the 2002 Design, 2002

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.

Chris C. N. Chu, Evangeline F. Y. Young

Proceedings of the 2002 Design, 2002

2001

On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.

Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Slicing floorplan with clustering constraints.

Wing Seung Yuen, Fung Yu Young

Proceedings of ASP-DAC 2001, 2001

2000

Slicing floorplans with range constraint.

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Floorplan area minimization using Lagrangian relaxation.

Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong

Proceedings of the 2000 International Symposium on Physical Design, 2000

1999

Slicing floorplans with boundary constraints.

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Generation of Universal Series-Parallel Boolean Functions.

Fung Yu Young, Chris C. N. Chu, D. F. Wong

J. ACM, 1999

Slicing floorplans with range constraint.

Fung Yu Young, D. F. Wong

Proceedings of the 1999 International Symposium on Physical Design, 1999

Integrated floorplanning and interconnect planning.

Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Slicing Floorplans with Boundary Constraint.

Fung Yu Young, D. F. Wong

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Slicing floorplans with pre-placed modules.

Fung Yu Young, D. F. Wong

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

How good are slicing floorplans?

F. Y. Young, D. F. Wong

Integr., 1997

On the Construction of Universal Series-Parallel Functions for Logic Module Design.

Fung Yu Young, D. F. Wong

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997