Feng Zhang

According to our database1, Feng Zhang authored at least 21 papers between 2008 and 2019.

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Bibliography

2019
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. on Circuits and Systems, 2019

2018
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection.
IEEE Trans. VLSI Syst., 2018

A 0.6V, 8.4uW AFE circuit for biomedical signal recording.
Microelectronics Journal, 2018

The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Wide-range tracking technique for process-variation-robust clock and data recovery applications.
Frontiers of IT & EE, 2017

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 128 Kb HfO2 ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement.
IEICE Electronic Express, 2016

A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A novel equalizer for the high-loss backplane at Nyquist frequency.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
An efficient physical coding sublayer for PCI express in 65nm CMOS.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Sinusoidal Clock Sampling for Multigigahertz ADCs.
IEEE Trans. on Circuits and Systems, 2011

A novel SST transmitter with mutually decoupled impedance self-calibration and equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A High Speed CMOS Transmitter and Rail-to-Rail Receiver.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008


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