Shubham Jain
Orcid: 0000-0002-2291-7712
According to our database1,
Shubham Jain
authored at least 31 papers
between 2016 and 2025.
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Bibliography
2025
CiMBA: Accelerating Genome Sequencing Through On-Device Basecalling via Compute-in-Memory.
IEEE Trans. Parallel Distributed Syst., June, 2025
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits, January, 2025
2024
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU.
IEEE Micro, 2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems.
ACM Trans. Embed. Comput. Syst., 2020
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.
Proc. IEEE, 2020
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks.
IEEE Trans. Computers, 2019
Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev., 2019
CoRR, 2019
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.
CoRR, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors.
Proceedings of the 55th Annual Design Automation Conference, 2018
2016
Approximation through logic isolation for the design of quality configurable circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016