Ying Wang

According to our database1, Ying Wang authored at least 52 papers between 2010 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.
IEEE Trans. VLSI Syst., 2019

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator.
Computer Architecture Letters, 2019

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.
SCIENCE CHINA Information Sciences, 2018

Caching or Not: Rethinking Virtual File System for Non-Volatile Main Memory.
Proceedings of the 10th USENIX Workshop on Hot Topics in Storage and File Systems, 2018

2017
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.
IEEE Trans. VLSI Syst., 2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. VLSI Syst., 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Power-Utility-Driven Write Management for MLC PCM.
JETC, 2017

Flip-flop clustering based trace signal selection for post-silicon debug.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR.
Proceedings of the 54th Annual Design Automation Conference, 2017

Dadu: Accelerating Inverse Kinematics for High-DOF Robots.
Proceedings of the 54th Annual Design Automation Conference, 2017

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.
Proceedings of the Computing Frontiers Conference, 2017

CNN-based object detection solutions for embedded heterogeneous multicore SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. VLSI Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.
IEEE Trans. VLSI Syst., 2016

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.
IEEE Trans. VLSI Syst., 2016

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.
Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.
Proceedings of the 53rd Annual Design Automation Conference, 2016

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Data Remapping for Static NUCA in Degradable Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.
IEEE Trans. VLSI Syst., 2015

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors.
IEEE Trans. VLSI Syst., 2015

A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electronic Express, 2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Retraining-based timing error mitigation for hardware neural networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

TURO: A lightweight turn-guided routing scheme for 3D NoCs.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Lightweight Timing Channel Protection for Shared Memory Controllers.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Reinventing Memory System Design for Many-Accelerator Architecture.
J. Comput. Sci. Technol., 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A low power DRAM refresh control scheme for 3D memory cube.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2013
Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
Proceedings of the Design, Automation and Test in Europe, 2011

Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
Proceedings of the 48th Design Automation Conference, 2011

2010
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010


  Loading...