Masahiro Fujita

Seyyedali Hosseinalipour

Jinjun Xiong

Bibhu Datta Sahoo

IEEE Internet Things J., April, 2025

RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits.

[BibT_eX]

[DOI]

Sanchari Das

Shiuh-Hua Wood Chiang

Kethireddy Harshith Reddy

Bibhu Datta Datta

IEEE Open J. Circuits Syst., 2025

Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications.

[BibT_eX]

[DOI]

Abhishek Yadav

Vyom Kumar Gupta

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Learned Image Codec on FPGA: Algorithm, Architecture and System Design.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

FPGA Codec System of Learned Image Compression With Algorithm-Architecture Co-Optimization.

[BibT_eX]

[DOI]

Heming Sun

Qingyang Yi

IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2024

Bidirectional LSTM Model for Accurate and Real-Time Landslide Detection: A Case Study in Mawiongrim, Meghalaya, India.

[BibT_eX]

[DOI]

IEEE Internet Things J., February, 2024

Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits -.

[BibT_eX]

[DOI]

Sanchari Das

Shiuh-Hua Wood Chiang

Bibhu Datta Sahoo

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Lightweight DL-based Drone Image Classification for Surveillance Applications.

[BibT_eX]

[DOI]

Abhishek Yadav

Proceedings of the 21st International SoC Design Conference, 2024

Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping.

[BibT_eX]

[DOI]

Abhishek Yadav

Proceedings of the 21st International SoC Design Conference, 2024

LLM-aided Front-End Design Framework For Early Development of Verified RTLs.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images.

[BibT_eX]

[DOI]

Bibhu Datta Sahoo

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

IIR Filter-Based Spiking Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Noise Resilience of Reduced Precision Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2022

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Approximating Arithmetic Circuits for IoT Devices Data Processing.

[BibT_eX]

[DOI]

Comput. Ind. Eng., 2022

Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

SAT-Based On-Track Bus Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Design of Single-Bit Fault-Tolerant Reversible Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

IEEE Trans. Circuits Syst., 2020

Theoretical Analysis of Noise Figure for Modulated Wideband Converter.

[BibT_eX]

[DOI]

Zolboo Byambadorj

Koji Asami

Takahiro J. Yamaguchi

Akio Higo

Tetsuya Iizuka

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2020

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints.

[BibT_eX]

[DOI]

Akihiro Goda

Yukio Miyasaka

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Real-Time Threshold-based Landslide Prediction System for Hilly Region using Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

LUT-based Circuit Approximation with Targeted Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Signal Selection Methods for Debugging Gate-Level Sequential Circuits.

[BibT_eX]

[DOI]

Yusuke Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.

[BibT_eX]

[DOI]

Virendra Singh

J. Electron. Test., 2019

An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.

[BibT_eX]

[DOI]

Virendra Singh

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Approximate Arithmetic Circuit Design Using a Fast and Scalable Method.

[BibT_eX]

[DOI]

Qi Lu

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Adder-Only Convolutional Neural Network with Binary Input Image.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

High-Level Engineering Change Through Programmable Datapath and SMT Solvers.

[BibT_eX]

[DOI]

Qinhao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Yukio Miyasaka

Akihiro Goda

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Signal Selection Methods for Efficient Multi-Target Correction.

[BibT_eX]

[DOI]

Yusuke Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.

[BibT_eX]

[DOI]

Conrad J. Moore

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

C Description Reconstruction Method from a Revised Netlist for ECO Support.

[BibT_eX]

[DOI]

Yusuke Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A New Reconfigurable Architecture with Applications to IoT and Mobile Computing.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018

2017

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A new approach for constructing logic functions after ECO.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Improving post-silicon error detection with topological selection of trace signals.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Testing multiple stuck-at faults of ROBDD based combinational circuit design.

[BibT_eX]

[DOI]

Toral Shah

Anzhela Yu. Matrosova

Virendra Singh

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Post-silicon observability enhancement with topology based trace signal selection.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

A new approach for selecting inputs of logic functions during debug.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A low-cost approximate 32-point transform architecture.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.

[BibT_eX]

[DOI]

Conrad J. Moore

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A new approach for diagnosing bridging faults in logic designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

RTL level trace signal selection and coverage estimation during post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Post Silicon Debugging of Electrical Bugs Using Trace Buffers.

[BibT_eX]

[DOI]

Kentaro Iwata

Mehdi Baradaran Tahoori

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Fast and Efficient Signature-Based Sub-Circuit Matching.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Efficient signature-based sub-circuit matching.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace signal selection methods for post silicon debugging.

[BibT_eX]

[DOI]

Shridhar Choudhary

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Temperature-aware software-based self-testing for delay faults.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Specification and formal verification of power gating in processors.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

Debugging processors with advanced features by reprogramming LUTs on FPGA.

[BibT_eX]

[DOI]

Satoshi Jo

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).

[BibT_eX]

[DOI]

Satoshi Jo

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Transaction Ordering in Network-on-Chips for Post-Silicon Validation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Time-Constraint-Aware Optimization of Assertions in Embedded Software.

[BibT_eX]

[DOI]

Viacheslav Izosimov

Giuseppe Di Guglielmo

J. Electron. Test., 2012

Transaction-based post-silicon debug of many-core System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Automatic rectification of design errors in complex processors with programmable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Global transaction ordering in Network-on-Chips for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Formal verification guided automatic design error diagnosis and correction of complex processors.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

Proceedings of the 16th European Test Symposium, 2011

2010

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).

[BibT_eX]

[DOI]

Bijan Alizadeh

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Pipelined Microprocessors Optimization and Debugging.

[BibT_eX]

[DOI]

Bijan Alizadeh

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Transaction-based debugging of system-on-chips with patterns.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Debugging from high level down to gate level.

[BibT_eX]

[DOI]

Yoshihisa Kojima

Proceedings of the 46th Design Automation Conference, 2009

1996

Solving the net matching problem in high-performance chip design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Simple tree-construction heuristics for the fanout problem .

[BibT_eX]

[DOI]

Robert J. Carragher

Chung-Kuan Cheng

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1993

An efficient algorithm for the net matching problem.

[BibT_eX]

[DOI]

Robert J. Carragher

Chung-Kuan Cheng