Katayoon Basharkhah

According to our database, Katayoon Basharkhah authored at least 12 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction.

Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi

Proceedings of the IEEE European Test Symposium, 2023

2021

Online Testing of a Row-Stationary Convolution Accelerator.

Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi

Proceedings of the 26th IEEE European Test Symposium, 2021

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester.

Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links.

Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator.

Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

An ESL Environment for Modeling Electrical Interconnect Faults.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization.

Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.

Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

A Comparison of MVDR and LCMV Beamformers' Floating Point Implementations on FPGAs.

Siavash Amin-Nejad, Tayyebeh Asgari Gashteroodkhani, Katayoon Basharkhah

Wirel. Pers. Commun., 2018