Jie Han

According to our database1, Jie Han authored at least 133 papers between 2000 and 2020.

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Bibliography

2020
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings.
IEEE Trans. Parallel Distributed Syst., 2020

Aggressive Fine-Grained Power Gating of NoC Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.
ACM Comput. Surv., 2020

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis.
IEEE Access, 2020

Dynamic Stochastic Computing for Digital Signal Processing Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.
IEEE Trans. Computers, 2019

A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology.
CoRR, 2019

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Approximate Arithmetic Circuits: Design and Evaluation.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Design, Evaluation and Application of Approximate High-Radix Dividers.
IEEE Trans. Multi Scale Comput. Syst., 2018

Automatic Selection of Process Corner Simulations for Faster Design Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation.
IEEE Trans. Computers, 2018

A stochastic approach for the reliability evaluation of multi-state systems with dependent components.
Reliab. Eng. Syst. Saf., 2018

An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation.
IEEE Access, 2018

A Probabilistic Error Model and Framework for Approximate Booth Multipliers.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and Application of an Approximate 2-D Convolver with Error Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Approximate On-chip Memory Optimization Method For Deep Residual Networks.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

An energy-efficient stochastic computational deep belief network.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems.
IEEE Trans. Parallel Distributed Syst., 2017

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).
IEEE Trans. Multi Scale Comput. Syst., 2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.
IEEE Trans. Computers, 2017

Two Approximate Voting Schemes for Reliable Computing.
IEEE Trans. Computers, 2017

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017

Approximate reliability of multi-state two-terminal networks by stochastic analysis.
IET Networks, 2017

A Stochastic Computational Approach for the Analysis of Fuzzy Systems.
IEEE Access, 2017

Design and operational assessment of an intra-cell hybrid L2 cache.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Partially universal modules for high performance logic circuit design.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Evaluating Data Resilience in CNNs from an Approximate Memory Perspective.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A true random number generator based on parallel STT-MTJs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy efficient stochastic computing with Sobol sequences.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware ODE Solvers using Stochastic Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

An efficient hardware design for cerebellar models using approximate circuits: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Logic-in-Memory With a Nonvolatile Programmable Metallization Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation.
IEEE Trans. Reliab., 2016

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.
IEEE Trans. Computers, 2016

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications.
IEEE Trans. Computers, 2016

Reliability and Criticality Analysis of Communication Networks by Stochastic Computation.
IEEE Netw., 2016

Design, evaluation and fault-tolerance analysis of stochastic FIR filters.
Microelectron. Reliab., 2016

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
Integr., 2016

A comparative evaluation of approximate multipliers.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A fully parallel approximate CORDIC design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Adaptive Filter Design Using Stochastic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

SRAM memory margin probability failure estimation using Gaussian Process regression.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Design and analysis of an approximate 2D convolver.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A novel gate grading approach for soft error tolerance in combinational circuits.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm.
ACM Trans. Reconfigurable Technol. Syst., 2015

A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures.
IEEE Trans. Reliab., 2015

Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory.
IEEE Trans. Multi Scale Comput. Syst., 2015

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Design and Analysis of Approximate Compressors for Multiplication.
IEEE Trans. Computers, 2015

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders.
IEEE Trans. Computers, 2015

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints.
Sci. China Inf. Sci., 2015

A Design Approach for Compressor Based Approximate Multipliers.
Proceedings of the 28th International Conference on VLSI Design, 2015

Design and evaluation of stochastic FIR filters.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Transmission gate-based approximate adders for inexact computing.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Matrix multiplication by an inexact systolic array.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM).
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Comparative Review and Evaluation of Approximate Adders.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Approximate compressors for error-resilient multiplier design.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Evaluating the impact of spike and flicker noise in phase change memories.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Minimizing the number of process corner simulations during design verification.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An approximate voting scheme for reliable computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Stochastic circuit design and performance evaluation of vector quantization.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates.
IEEE Trans. Reliab., 2014

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation.
IEEE Trans. Computers, 2014

Stochastic Multiple-Valued Gene Networks.
IEEE Trans. Biomed. Circuits Syst., 2014

Robust HSPICE modeling of a single electron turnstile.
Microelectron. J., 2014

Asynchronous Stochastic Boolean Networks as Gene Network Models.
J. Comput. Biol., 2014

Gene perturbation and intervention in context-sensitive stochastic Boolean networks.
BMC Syst. Biol., 2014

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A memristor-based TCAM (Ternary Content Addressable Memory) cell.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

FDSOI SRAM cells for low power design at 22nm technology node.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A system-level scheme for resistance drift tolerance of a multilevel phase change memory.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A low-power, high-performance approximate multiplier with configurable partial error recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

New Metrics for the Reliability of Approximate and Probabilistic Adders.
IEEE Trans. Computers, 2013

Analysis of Error Masking and Restoring Properties of Sequential Circuits.
IEEE Trans. Computers, 2013

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration.
J. Syst. Archit., 2013

A PCM-based TCAM cell using NDR.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks.
BMC Syst. Biol., 2012

Cell design and comparative evaluation of a novel 1T memristor-based memory.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Macromodeling a phase change memory (PCM) cell by HSPICE.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Modeling a single electron turnstile in HSPICE.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Hardening a memory cell for low power operation by gate leakage reduction.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Reliability evaluation of logic circuits using probabilistic gate models.
Microelectron. Reliab., 2011

A hybrid memory cell using Single-Electron transfer.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Reliable Performance of Sequential Adders for Soft Computing.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Stochastic computational models for accurate reliability evaluation of logic circuits.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2005
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics.
IEEE Des. Test Comput., 2005

Faults, Error Bounds and Reliability of Nanoelectronic Circuits.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers.
Proceedings of the 17th International Conference on Pattern Recognition, 2004

2003
A Study on Fault-Tolerant Circuits Using Redundancy.
Proceedings of the International Conference on VLSI, 2003

2000
On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000


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