Srinivas Devadas

According to our database1, Srinivas Devadas authored at least 316 papers between 1986 and 2018.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2014, "For contributions to secure and energy-efficient hardware.".

IEEE Fellow

IEEE Fellow 1998, "For contributions to logic design and design automation.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2018
Sundial: Harmonizing Concurrency Control and Caching in a Distributed OLTP Database Management System.
PVLDB, 2018

Path ORAM: An Extremely Simple Oblivious RAM Protocol.
J. ACM, 2018

Transparency Logs via Append-only Authenticated Dictionaries.
IACR Cryptology ePrint Archive, 2018

Secure Boot and Remote Attestation in the Sanctum Processor.
IACR Cryptology ePrint Archive, 2018

DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors.
IACR Cryptology ePrint Archive, 2018

Synchronous Byzantine Agreement with Expected O(1) Rounds, Expected O(n2) Communication, and Optimal Resilience.
IACR Cryptology ePrint Archive, 2018

Var-CNN and DynaFlow: Improved Attacks and Defenses for Website Fingerprinting.
CoRR, 2018

DynaFlow: An Efficient Website Fingerprinting Defense Based on Dynamically-Adjusting Flows.
Proceedings of the 2018 Workshop on Privacy in the Electronic Society, 2018

Mission Assurance: Beyond Secure Processing.
Proceedings of the 2018 IEEE International Conference on Software Quality, 2018

Invited Paper: Secure Boot and Remote Attestation in the Sanctum Processor.
Proceedings of the 31st IEEE Computer Security Foundations Symposium, 2018

2017
Trapdoor Computational Fuzzy Extractors and Stateless Cryptographically-Secure Physical Unclonable Functions.
IEEE Trans. Dependable Sec. Comput., 2017

A Formal Foundation for Secure Remote Execution of Enclaves.
IACR Cryptology ePrint Archive, 2017

Practical Synchronous Byzantine Consensus.
IACR Cryptology ePrint Archive, 2017

Bandwidth Hard Functions for ASIC Resistance.
IACR Cryptology ePrint Archive, 2017

Public Key Cryptosystems with Noisy Secret Keys.
IACR Cryptology ePrint Archive, 2017

On Iterative Collision Search for LPN and Subset Sum.
IACR Cryptology ePrint Archive, 2017

Secure Processors Part II: Intel SGX Security Analysis and MIT Sanctum Architecture.
Foundations and Trends in Electronic Design Automation, 2017

Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture.
Foundations and Trends in Electronic Design Automation, 2017

FPGA Implementation of a Cryptographically-Secure PUF Based on Learning Parity with Noise.
Cryptography, 2017

Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation.
CoRR, 2017

Practical Synchronous Byzantine Consensus.
CoRR, 2017

PriviPK: Certificate-less and secure email communication.
Computers & Security, 2017

Pervasive, dynamic authentication of physical items.
Commun. ACM, 2017

Brief Announcement: Practical Synchronous Byzantine Consensus.
Proceedings of the 31st International Symposium on Distributed Computing, 2017

On Iterative Collision Search for LPN and Subset Sum.
Proceedings of the Theory of Cryptography - 15th International Conference, 2017

Bandwidth Hard Functions for ASIC Resistance.
Proceedings of the Theory of Cryptography - 15th International Conference, 2017

Catena: Efficient Non-equivocation via Bitcoin.
Proceedings of the 2017 IEEE Symposium on Security and Privacy, 2017

Atom: Horizontally Scaling Strong Anonymity.
Proceedings of the 26th Symposium on Operating Systems Principles, 2017

Leveraging Hardware Isolation for Process Level Access Control & Authentication.
Proceedings of the 22nd ACM on Symposium on Access Control Models and Technologies, 2017

Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Using Application-Level Thread Progress Information to Manage Power and Performance.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Formal Foundation for Secure Remote Execution of Enclaves.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, CCS 2017, Dallas, TX, USA, October 30, 2017

Secure Hardware and Cryptography: Contrasts, Synergies and Challenges.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

2016
A Lockdown Technique to Prevent Machine Learning on PUFs for Lightweight Authentication.
IEEE Trans. Multi-Scale Computing Systems, 2016

Locality-aware data replication in the last-level cache for large scale multicores.
The Journal of Supercomputing, 2016

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.
TACO, 2016

Pervasive, Dynamic Authentication of Physical Items.
ACM Queue, 2016

Riffle: An Efficient Communication System With Strong Anonymity.
PoPETs, 2016

Catena: Preventing Lies with Bitcoin.
IACR Cryptology ePrint Archive, 2016

Beaver: A Decentralized Anonymous Marketplace with Secure Reputation.
IACR Cryptology ePrint Archive, 2016

Proof of Space from Stacked Bipartite Graphs.
IACR Cryptology ePrint Archive, 2016

Intel SGX Explained.
IACR Cryptology ePrint Archive, 2016

Atom: Scalable Anonymity Resistant to Traffic Analysis.
CoRR, 2016

Sanctum: Minimal Hardware Extensions for Strong Software Isolation.
Proceedings of the 25th USENIX Security Symposium, 2016

Proof of Space from Stacked Expanders.
Proceedings of the Theory of Cryptography - 14th International Conference, 2016

Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM.
Proceedings of the Theory of Cryptography - 13th International Conference, 2016

TicToc: Time Traveling Optimistic Concurrency Control.
Proceedings of the 2016 International Conference on Management of Data, 2016

Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Onion ORAM: A Constant Bandwidth and Constant Client Storage ORAM (without FHE or SWHE).
IACR Cryptology ePrint Archive, 2015

Sanctum: Minimal RISC Extensions for Isolated Execution.
IACR Cryptology ePrint Archive, 2015

A Proof of Correctness for the Tardis Cache Coherence Protocol.
CoRR, 2015

Tardis 2.0: An Optimized Time Traveling Coherence Protocol.
CoRR, 2015

TARDIS: Timestamp based Coherence Algorithm for Distributed Shared Memory.
CoRR, 2015

The Execution Migration Machine: Directoryless Shared-Memory Architecture.
IEEE Computer, 2015

Constants Count: Practical Improvements to Oblivious RAM.
Proceedings of the 24th USENIX Security Symposium, 2015

Circuit Fingerprinting Attacks: Passive Deanonymization of Tor Hidden Services.
Proceedings of the 24th USENIX Security Symposium, 2015

IMP: indirect memory prefetcher.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

PrORAM: dynamic prefetcher for oblivious RAM.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A Low-Latency, Low-Area Hardware Oblivious RAM Controller.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory.
Proceedings of the 2015 International Conference on Parallel Architecture and Compilation, 2015

OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.
Proceedings of the 2015 International Conference on Parallel Architecture and Compilation, 2015

2014
Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching.
IEEE Trans. Emerging Topics Comput., 2014

Staring into the Abyss: An Evaluation of Concurrency Control with One Thousand Cores.
PVLDB, 2014

Physical Unclonable Functions and Applications: A Tutorial.
Proceedings of the IEEE, 2014

Simultaneous Alignment and Folding of Protein Sequences.
Journal of Computational Biology, 2014

Enhancing Oblivious RAM Performance Using Dynamic Prefetching.
IACR Cryptology ePrint Archive, 2014

Unified Oblivious-RAM: Improving Recursive ORAM with Locality and Pseudorandomness.
IACR Cryptology ePrint Archive, 2014

Ring ORAM: Closing the Gap Between Small and Large Client Storage Oblivious RAM.
IACR Cryptology ePrint Archive, 2014

Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines.
IACR Cryptology ePrint Archive, 2014

Trapdoor Computational Fuzzy Extractors.
IACR Cryptology ePrint Archive, 2014

RAW Path ORAM: A Low-Latency, Low-Area Hardware ORAM Controller with Integrity Verification.
IACR Cryptology ePrint Archive, 2014

Thread Migration Prediction for Distributed Shared Caches.
Computer Architecture Letters, 2014

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation.
Proceedings of the Symposium on VLSI Circuits, 2014

Power modeling and other new features in the Graphite simulator.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Author retrospective for analytical cache models with applications to cache partitioning.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Algorithms for scheduling task-based applications onto heterogeneous many-core architectures.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Low-overhead hard real-time aware interconnect network router.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Locality-aware data replication in the Last-Level Cache.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

A noise bifurcation architecture for linear additive physical functions.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013
PUF Modeling Attacks on Simulated and Silicon Data.
IEEE Trans. Information Forensics and Security, 2013

Optimal and Heuristic Application-Aware Oblivious Routing.
IEEE Trans. Computers, 2013

Path ORAM: An Extremely Simple Oblivious RAM Protocol.
IACR Cryptology ePrint Archive, 2013

PUF Modeling Attacks on Simulated and Silicon Data.
IACR Cryptology ePrint Archive, 2013

Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors.
IACR Cryptology ePrint Archive, 2013

Toward a Coherent Multicore Memory Model.
IEEE Computer, 2013

A framework to accelerate sequential programs on homogeneous multicores.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Design space exploration and optimization of path oblivious RAM in secure processors.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

The locality-aware adaptive cache coherence protocol.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Integrity verification for path Oblivious-RAM.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

Hardware-level thread migration in a 110-core shared-memory multiprocessor.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Heracles: a tool for fast RTL-based design space exploration of multicore processors.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

MARTHA: architecture for control and emulation of power electronics and smart grid systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Generalized external interaction with tamper-resistant hardware with bounded information leakage.
Proceedings of the CCSW'13, 2013

Authenticated storage using small trusted hardware.
Proceedings of the CCSW'13, 2013

Path ORAM: an extremely simple oblivious RAM protocol.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012
Selecting Spatiotemporal Patterns for Development of Parallel Applications.
IEEE Trans. Parallel Distrib. Syst., 2012

HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Compilation Techniques for Efficient Encrypted Computation.
IACR Cryptology ePrint Archive, 2012

Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching.
Proceedings of the 2012 IEEE Symposium on Security and Privacy Workshops, 2012

Lynx: A Programmatic SAT Solver for the RNA-Folding Problem.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Performance metrics and empirical results of a PUF cryptographic key generation ASIC.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Self-aware computing in the Angstrom processor.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Towards an interpreter for efficient encrypted computation.
Proceedings of the 2012 ACM Workshop on Cloud computing security, 2012

A low-overhead dynamic optimization framework for multicores.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Efficient Traversal of Beta-Sheet Protein Folding Pathways Using Ensemble Models.
Journal of Computational Biology, 2011

DCC: A Dependable Cache Coherence Multicore Architecture.
Computer Architecture Letters, 2011

A method for probing the mutational landscape of amyloid structure.
Bioinformatics [ISMB/ECCB], 2011

Brief announcement: distributed shared memory based on computation migration.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

Efficient Traversal of Beta-Sheet Protein Folding Pathways Using Ensemble Models.
Proceedings of the Research in Computational Molecular Biology, 2011

Deadlock-free fine-grained thread migration.
Proceedings of the NOCS 2011, 2011

Scalable, accurate multicore simulation in the 1000-core era.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Memory coherence in the age of multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Reliable and efficient PUF-based key generation using pattern matching.
Proceedings of the HOST 2011, 2011

Security challenges and opportunities in adaptive and reconfigurable hardware.
Proceedings of the HOST 2011, 2011

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Lightweight and Secure PUF Key Storage Using Limits of Machine Learning.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Modeling Attacks on Physical Unclonable Functions.
IACR Cryptology ePrint Archive, 2010

Secure and Robust Error Correction for Physical Unclonable Functions.
IEEE Design & Test of Computers, 2010

FPGA PUF using programmable delay lines.
Proceedings of the 2010 IEEE International Workshop on Information Forensics and Security, 2010

Modeling attacks on physical unclonable functions.
Proceedings of the 17th ACM Conference on Computer and Communications Security, 2010

2009
RNAmutants: a web server to explore the mutational landscape of RNA secondary structures.
Nucleic Acids Research, 2009

Efficient stochastic simulation of reaction-diffusion processes via direct compilation.
Bioinformatics, 2009

Simultaneous Alignment and Folding of Protein Sequences.
Proceedings of the Research in Computational Molecular Biology, 2009

Static virtual channel allocation in oblivious routing.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Path-based, randomized, oblivious, minimal routing.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Application-aware deadlock-free oblivious routing.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.
Proceedings of the PACT 2009, 2009

2008
Controlled physical random functions and applications.
ACM Trans. Inf. Syst. Secur., 2008

Efficient Algorithms for Probing the RNA Mutation Landscape.
PLoS Computational Biology, 2008

Offline count-limited certificates.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Diastolic arrays: throughput-driven reconfigurable computing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

The Trusted Execution Module: Commodity General-Purpose Trusted Computing.
Proceedings of the Smart Card Research and Advanced Applications, 2008

2007
Aegis: A Single-Chip Secure Processor.
IEEE Design & Test of Computers, 2007

Learning biophysically-motivated parameters for alpha helix prediction.
BMC Bioinformatics, 2007

Physical Unclonable Functions for Device Authentication and Secret Key Generation.
Proceedings of the 44th Design Automation Conference, 2007

Offline untrusted storage with immediate detection of forking and replay attacks.
Proceedings of the 2nd ACM Workshop on Scalable Trusted Computing, 2007

2006
Speeding up Exponentiation using an Untrusted Computational Resource.
Des. Codes Cryptography, 2006

Knowledge Flow Analysis for Security Protocols
CoRR, 2006

A Generalized Two-Phase Analysis of Knowledge Flows in Security Protocols
CoRR, 2006

Predicting Secondary Structure of All-Helical Proteins Using Hidden Markov Support Vector Machines.
Proceedings of the Pattern Recognition in Bioinformatics, International Workshop, 2006

Virtual monotonic counters and count-limited objects using a TPM without a trusted OS.
Proceedings of the 1st ACM Workshop on Scalable Trusted Computing, 2006

2005
Extracting secret keys from integrated circuits.
IEEE Trans. VLSI Syst., 2005

AEGIS: A single-chip secure processor.
Inf. Sec. Techn. Report, 2005

Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data.
Proceedings of the 2005 IEEE Symposium on Security and Privacy (S&P 2005), 2005

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Dynamic Partitioning of Shared Cache Memory.
The Journal of Supercomputing, 2004

Power Estimation Using Probability Polynomials.
Design Autom. for Emb. Sys., 2004

Access-controlled resource discovery in pervasive networks.
Concurrency - Practice and Experience, 2004

Identification and authentication of integrated circuits.
Concurrency - Practice and Experience, 2004

Rate Guarantees and Overload Protection in Input-Queued Switches.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

Secure program execution via dynamic information flow tracking.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Techniques for accurate performance evaluation in architecture exploration.
IEEE Trans. VLSI Syst., 2003

Access-Controlled Resource Discovery for Pervasive Networks.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Delay-Based Circuit Authentication and Applications.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Efficient Memory Integrity Verification and Encryption for Secure Processors.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

AEGIS: architecture for tamper-evident and tamper-resistant processing.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Caches and Hash Trees for Efficient Memory Integrity Verification.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Embedded intelligent SRAM.
Proceedings of the 40th Design Automation Conference, 2003

Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking.
Proceedings of the Advances in Cryptology - ASIACRYPT 2003, 9th International Conference on the Theory and Application of Cryptology and Information Security, Taipei, Taiwan, November 30, 2003

2002
Functional vector generation for sequential HDL models under an observability-based code coverage metric.
IEEE Trans. VLSI Syst., 2002

Proxy-based security protocols in networked mobile devices.
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

The Untrusted Computer Problem and Camera-Based Authentication.
Proceedings of the Pervasive Computing, 2002

A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Silicon physical random functions.
Proceedings of the 9th ACM Conference on Computer and Communications Security, 2002

Controlled Physical Random Functions.
Proceedings of the 18th Annual Computer Security Applications Conference (ACSAC 2002), 2002

2001
OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Effects of Memory Performance on Parallel Job Scheduling.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2001

Analytical cache models with applications to cache partitioning.
Proceedings of the 15th international conference on Supercomputing, 2001

Software-Assisted Cache Replacement Mechanisms for Embedded Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Solving covering problems using LPR-based lower bounds.
IEEE Trans. VLSI Syst., 2000

ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration.
Design Autom. for Emb. Sys., 2000

Observability Analysis of Embedded Software for Coverage-Directed Validation.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Application-specific memory management for embedded systems using software-controlled caches.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A text-compression-based method for code size minimization in embedded systems.
ACM Trans. Design Autom. Electr. Syst., 1999

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures.
Design Autom. for Emb. Sys., 1999

CAD Techniques for Embedded System Design.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Methodology for Accurate Performance Evaluation in Architecture Exploration.
Proceedings of the 36th Conference on Design Automation, 1999

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A low power, low bandwidth protocol for remote wireless terminals.
Wireless Networks, 1998

A new viewpoint on code generation for directed acyclic graphs.
ACM Trans. Design Autom. Electr. Syst., 1998

BDD-based synthesis of extended burst-mode controllers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Sequential logic optimization for low power using input-disabling precomputation architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Code density optimization for embedded DSP processors using data compression techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Power Estimation Under User-Specified Input Sequences and Programs.
Integrated Computer-Aided Engineering, 1998

Code Optimization Techniques in Embedded DSP Microprocessors.
Design Autom. for Emb. Sys., 1998

An algorithmic approach to optimizing fault coverage for BIST logic synthesis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.
Proceedings of the 35th Conference on Design Automation, 1998

OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.
Proceedings of the 35th Conference on Design Automation, 1998

Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Estimation of average switching activity in combinational logic circuits using symbolic simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Switching activity estimation using limited depth reconvergent path analysis.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures.
Proceedings of the 34st Conference on Design Automation, 1997

Solving Covering Problems Using LPR-Based Lower Bounds.
Proceedings of the 34st Conference on Design Automation, 1997

ISDL: An Instruction Set Description Language for Retargetability.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Techniques for power estimation and optimization at the logic level: A survey.
VLSI Signal Processing, 1996

Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. VLSI Syst., 1996

Storage Assignment to Decrease Code Size.
ACM Trans. Program. Lang. Syst., 1996

Addendum to "Synthesis of robust delay-fault testable circuits: Theory".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

An observability-based code coverage metric for functional simulation.
ICCAD, 1996

Scheduling Techniques to Enable Power Management.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Power estimation methods for sequential logic circuits.
IEEE Trans. VLSI Syst., 1995

Probabilistic manipulation of Boolean functions using free Boolean diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Storage Assignment to Decrease Code Size.
Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), 1995

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Instruction selection using binate covering for code size optimization.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Code Optimization Techniques for Embedded DSP Microprocessors.
Proceedings of the 32st Conference on Design Automation, 1995

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Optimization of combinational and sequential logic circuits for low power using precomputation.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

Code density optimization for embedded DSP processors using data compression techniques.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Verification of asynchronous interface circuits with bounded wire delays.
VLSI Signal Processing, 1994

Certified timing verification and the transition delay of a logic circuit.
IEEE Trans. VLSI Syst., 1994

Precomputation-based sequential logic optimization for low power.
IEEE Trans. VLSI Syst., 1994

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Bitwise Encoding of Finite State Machines.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Performance-driven synthesis of asynchronous controllers.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Precomputation-based sequential logic optimization for low power.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Challenges in code generation for embedded processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Automatic Verification of Pipelined Microprocessors.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Statistical timing analysis of combinational logic circuits.
IEEE Trans. VLSI Syst., 1993

Sequential test generation and synthesis for testability at the register-transfer and logic levels.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Computation of floating mode delay in combinational circuits: practice and implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Computation of floating mode delay in combinational circuits: theory and algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Comparing two-level and ordered binary decision diagram representations of logic functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Delay-fault test generation and synthesis for testability under a standard scan design methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Verification of relations between synchronous machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Path-delay-fault testability properties of multiplexor-based networks.
Integration, 1993

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.
Formal Methods in System Design, 1993

Guest editorial.
J. Electronic Testing, 1993

A synthesis-based test generation and compaction algorithm for multifaults.
J. Electronic Testing, 1993

Probabilistic construction and manipulation of free Boolean diagrams.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Retiming sequential circuits for low power.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Boolean factorization using multiple-valued minimization.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Heuristic minimization of Boolean relations using testing techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Validatable nonrobust delay-fault testable circuits via logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Synthesis of robust delay-fault-testable circuits: practice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Synthesis of robust delay-fault-testable circuits: theory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams.
Integration, 1992

Statistical Timing Analysis of Combinational Circuits.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On average power dissipation and random pattern testability of CMOS combinational logic networks.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Verification of asynchronous interface circuits with bounded wire delays.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Automatic generation and verification of sufficient correctness properties for synchronous processors.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Estimation of Average Switching Activity in Combinational and Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

Certified Timing Verification and the Transition Delay of a Logic Circuit.
Proceedings of the 29th Design Automation Conference, 1992

1991
Test generation and verification for highly sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Exact algorithms for output encoding, state assignment, and four-level Boolean minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

A unified approach to the synthesis of fully testable sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Optimizing interacting finite state machines using sequential don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Irredundant interacting sequential machines via optimal logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Optimum and heuristic algorithms for an approach to finite state machine decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

An automata-theoretic approach to behavioral equivalence.
Integration, 1991

Recent progress in synthesis for testability.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Design Verfication and Reachability Analysis Using Algebraic Manipulation.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Finite State Machine Decomposition by Transition Pairing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Delay Computation in Combinational Logic Circuits: Theory and Algorithms.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Verification of Relations Between Synchronous Machines.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults.
Proceedings of the 28th Design Automation Conference, 1991

Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology.
Proceedings of the 28th Design Automation Conference, 1991

1990
Irredundant sequential machines via optimal logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Easily testable PLA-based finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Redundancies and don't cares in sequential logic synthesis.
J. Electronic Testing, 1990

Sequential logic synthesis for testability using register-transfer level descriptions.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Design of integrated circuits fully testable for delay-faults and multifaults.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Minimization of Functions with Multiple-Valued Outputs: Theory and Applications.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

Heuristic minimization of Boolean relations using testing techniques.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Testability driven synthesis of interacting finite state machines.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

An Automata-Theoretic Approach to Behavioral Equivalence.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Testability-Preserving Circuit Transformations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Sequential Test Generation at the Register-Transfer and Logic Levels.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Verification of Interacting Sequential Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Logic verification algorithms and their parallel implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Decomposition and factorization of sequential finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Algorithms for hardware allocation in data path synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

A synthesis and optimization procedure for fully and easily testable sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Redundancies and Don't Cares in Sequential Logic Synthesis.
Proceedings of the Proceedings International Test Conference 1989, 1989

Delay Test Generation for Synchronous Sequential Circuits.
Proceedings of the Proceedings International Test Conference 1989, 1989

Test generation for highly sequential circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Boolean minimization and algebraic factorization procedures for fully testable sequential machines.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Optimal layout via Boolean satisfiability.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Optimum and heuristic algorithms for finite state machine decomposition and partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Easily testable PLA-based finite state machines.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

General Decomposition of Sequential Machines: Relationships to State Assignment.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Approaches to Multi-level Sequential Logic Synthesis.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Test generation for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

On the verification of sequential machines at differing levels of abstraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Techniques for multilayer channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
Proceedings of the Proceedings International Test Conference 1988, 1988

Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.
Proceedings of the Proceedings International Test Conference 1988, 1988

Boolean decomposition in multi-level logic optimization.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Decomposition and factorization of sequential finite state machines.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Topological Optimization of Multiple-Level Array Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

Logic Verification Algorithms and Their Parallel Implementation.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

On the Verification of Sequential Machines at Differing Levels of Abstraction.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
GENIE: a generalized array optimizer for VLSI synthesis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Chameleon: a new multi-layer channel router.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986


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