Victor V. Zyuban

According to our database, Victor V. Zyuban authored at least 38 papers between 1998 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban

IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.

Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny

IBM J. Res. Dev., 2015

Session 8 overview: Low-power digital techniques: Energy-efficient digital.

Victor V. Zyuban, Peter Nilsson

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

5.1 POWER8^TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.

Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The POWER8^TM processor: Designed for big data, analytics, and cloud environments.

Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

POWER8 design methodology innovations for improving productivity and reducing power.

Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

IBM POWER7+ design for higher frequency at fixed power.

Victor V. Zyuban, Scott A. Taylor, Birger Christensen, A. R. Hall, Christopher J. Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, Rajeev R. Rao

IBM J. Res. Dev., 2013

Runtime power reduction capability of the IBM POWER7+ chip.

Michael S. Floyd, Alan J. Drake, Nicole S. Schwartz, Robert W. Berry, Charles Lefurgy, Malcolm S. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, Ruby M. Zgabay

IBM J. Res. Dev., 2013

Power reduction by aggressive synthesis design space exploration.

Matthew M. Ziegler, George Gristede, Victor V. Zyuban

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.

Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2011

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban

IEEE J. Solid State Circuits, 2011

2010

The implementation of POWER7^TM: A highly parallel and scalable multi-core high-end server processor.

Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

POWER7^TM local clocking and clocked storage elements.

James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.

Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

The opportunity cost of low power design: a case study in circuit tuning.

Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.

Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

A Framework for Architecture-Level Lifetime Reliability Modeling.

Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2005

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.

Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.

Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

Integrated Analysis of Power and Performance for Pipelined Microprocessors.

Victor V. Zyuban, David M. Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma

IEEE Trans. Computers, 2004

Microarchitectural techniques for power gating of execution units.

Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Design methodology for semi custom processor cores.

Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

Optimization of scannable latches for low energy.

Victor V. Zyuban

IEEE Trans. Very Large Scale Integr. Syst., 2003

Balancing hardware intensity in microprocessor pipelines.

Victor V. Zyuban, Philip N. Strenski

IBM J. Res. Dev., 2003

An innovative low-power high-performance programmable signal processor for digital communications.

Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter

IBM J. Res. Dev., 2003

Low-power circuits and technology for wireless digital systems.

Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban

IBM J. Res. Dev., 2003

2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.

Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas

Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Optimizing pipelines for power and performance.

Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.

Victor V. Zyuban, Philip N. Strenski

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Low power integrated scan-retention mechanism.

Victor V. Zyuban, Stephen V. Kosonocky

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Unified architecture level energy-efficiency metric.

Victor V. Zyuban

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Inherently Lower-Power High-Performance Superscalar Architectures.

Victor V. Zyuban, Peter M. Kogge

IEEE Trans. Computers, 2001

Clocking strategies and scannable latches for low power appliacations.

Victor V. Zyuban, David Meltzer

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.

David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook

IEEE Micro, 2000

Optimization of high-performance superscalar architectures for energy efficiency.

Victor V. Zyuban, Peter M. Kogge

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999

Application of STD to latch-power estimation.

Victor V. Zyuban, Peter M. Kogge

IEEE Trans. Very Large Scale Integr. Syst., 1999

1998

The energy complexity of register files.

Victor V. Zyuban, Peter M. Kogge

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998