Kenichi Okada
Orcid: 0000-0002-1082-7672Affiliations:
- Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Tokyo, Japan
- Kyoto University, Department of Communications and Computer Engineering, Kyoto, Japan (PhD 2003)
According to our database1,
Kenichi Okada
authored at least 274 papers
between 2000 and 2025.
Collaborative distances:
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Bibliography
2025
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur.
IEEE J. Solid State Circuits, June, 2025
IEEE J. Solid State Circuits, April, 2025
A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference.
IEEE J. Solid State Circuits, March, 2025
A 2.5 dB noise figure 28 GHz current-reused noise-cancelling LNA with g<sub>m</sub>-boosting in 65 nm CMOS for millimeter-wave MIMO applications.
IEICE Electron. Express, 2025
A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor.
IEEE Access, 2025
A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation.
IEEE Access, 2025
NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers.
IEEE Access, 2025
Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power Transmission.
Proceedings of the 16th IEEE Latin America Symposium on Circuits and Systems, 2025
5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
IEEE J. Solid State Circuits, May, 2024
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter.
IEEE J. Solid State Circuits, April, 2024
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.
IEEE J. Solid State Circuits, April, 2024
A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation.
IEEE J. Solid State Circuits, February, 2024
IPSJ Trans. Syst. LSI Des. Methodol., 2024
Millimeter-Wave Transceiver Utilizing On-Chip Butler Matrix for Simultaneous 5G Relay Communication and Wireless Power Transfer.
IEICE Trans. Electron., 2024
A synthesizable spread spectrum clock generator based on type-II/III fractional-<i>N</i> DPLL.
IEICE Electron. Express, 2024
A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024
A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations.
IEEE J. Solid State Circuits, December, 2023
A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD.
IEEE J. Solid State Circuits, October, 2023
A 28GHz High-Accuracy Phase and Amplitude Detection Circuit for Dual-Polarized Phased-Array Calibration.
IEICE Trans. Electron., April, 2023
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station.
IEEE J. Solid State Circuits, 2023
A 41-GHz 19.4-dBm P<sub>sat</sub> CMOS Doherty power amplifier for 5G NR applications.
IEICE Electron. Express, 2023
A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount.
IEEE Access, 2023
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Dual-Mode Bi-Directional CMOS Mixer Using Push-Push Doubler for 300GHz-Band Transceivers.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 24-49-GHz CMOS Area-Efficient Phase-Invariant Mixed-Type Attenuator With Capacitive Compensation for 5G New Radio.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
An 8.5-dB Insertion Loss and 0.8° RMS Phase Error Ka-Band CMOS Hybrid Phase Shifter Featuring Nonuniform Matching for Satellite Communication.
IEICE Trans. Electron., October, 2022
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR.
IEEE J. Solid State Circuits, 2022
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.
IEEE J. Solid State Circuits, 2022
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer.
IEEE J. Solid State Circuits, 2022
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation.
IEEE J. Solid State Circuits, 2022
A 0.37mm<sup>2</sup> Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components.
IEICE Trans. Electron., 2022
A Compact and High-Resolution CMOS Switch-Type Phase Shifter Achieving 0.4-dB RMS Gain Error for 5G n260 Band.
IEICE Trans. Electron., 2022
F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power.
IEICE Trans. Electron., 2022
Performance Evaluation of Classification and Verification with Quadrant IQ Transition Image.
IEICE Trans. Commun., 2022
IEICE Electron. Express, 2022
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing Technique.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G.
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022
2021
A 0.85mm<sup>2</sup> BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth.
IEEE J. Solid State Circuits, 2021
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems.
IEEE J. Solid State Circuits, 2021
IEICE Electron. Express, 2021
A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 0.25 mm<sup>2</sup> BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration.
Proceedings of the 47th ESSCIRC 2021, 2021
28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications.
IEICE Trans. Electron., 2020
A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio.
IEICE Trans. Electron., 2020
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
A Compact 37-40GHz CMOS Switch-Type Phase Shifter with Fine-Tuning Stage Achieving 0.4-dB RMS Gain Error.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Millimeter-Wave CMOS Phased-Array Transceiver Supporting Dual-Polarized MIMO for 5G NR.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IEEE J. Solid State Circuits, 2019
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio.
IEEE J. Solid State Circuits, 2019
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
IEICE Trans. Electron., 2019
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.
IEICE Trans. Electron., 2019
IEICE Trans. Electron., 2019
0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10<sup>-12</sup> Long-Term Allan Deviation Using Cesium Coherent Population Trapping.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019
300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology.
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS.
IEICE Trans. Electron., 2018
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS.
IEICE Trans. Electron., 2018
IEICE Electron. Express, 2018
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.85mm<sup>2</sup> BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS.
IEICE Trans. Electron., 2017
IEICE Trans. Electron., 2017
IEICE Trans. Commun., 2017
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
IEEE J. Solid State Circuits, 2016
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016
A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2015
Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.
IEEE J. Solid State Circuits, 2015
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections.
IEICE Trans. Electron., 2015
Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Electron., 2015
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit.
IEICE Trans. Electron., 2015
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI.
IEICE Electron. Express, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process.
Proceedings of the 45th European Solid State Device Research Conference, 2015
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.
Proceedings of the ESSCIRC Conference 2015, 2015
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits, 2014
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios.
IEEE J. Solid State Circuits, 2014
A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation.
IEICE Trans. Electron., 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
15.1 A 0.0066mm<sup>2</sup> 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the ESSCIRC 2014, 2014
A 0.015-mm<sup>2</sup> 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 0.011 mm<sup>2</sup> PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.
IEEE J. Solid State Circuits, 2013
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers.
IEEE J. Solid State Circuits, 2013
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing.
IEEE J. Solid State Circuits, 2013
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate.
IEICE Electron. Express, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 0.022mm<sup>2</sup> 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs.
Proceedings of the ESSCIRC 2013, 2013
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition.
IEICE Trans. Electron., 2012
Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Electron., 2012
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications.
IEEE J. Solid State Circuits, 2011
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers.
J. Electr. Comput. Eng., 2011
Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate.
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving.
IEICE Trans. Electron., 2011
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Electron. Express, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International SoC Design Conference, 2011
A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling.
IEICE Trans. Electron., 2010
Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators.
IEICE Trans. Electron., 2010
Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider.
IEICE Trans. Electron., 2010
The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators.
IEICE Trans. Electron., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Prediction of delay time for future LSI using on-chip transmission line interconnects.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEICE Electron. Express, 2004
High speed and low power on-chip micro network circuit with differential transmission line.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
Modelling and optimization of on-chip spiral inductor in S-parameter domain.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Design, 2004
Differential transmission line interconnect for high speed and low power global wiring.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Statistical modeling of gate-delay variation with consideration of intra-gate variability.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of ASP-DAC 2000, 2000