Xiaowei Li

According to our database1, Xiaowei Li authored at least 294 papers between 1998 and 2019.

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2019
SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks.
ACM Trans. Design Autom. Electr. Syst., 2019

ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks.
IEEE Trans. Computers, 2019

PUFPass: A password management mechanism based on software/hardware codesign.
Integration, 2019

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator.
Computer Architecture Letters, 2019

BZIP: A Compact Data Memory System for UTXO-based Blockchains.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Redeeming chip-level power efficiency by collaborative management of the computation and communication.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

TNPU: an efficient accelerator architecture for training convolutional neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

P3M: a PIM-based neural network model protection scheme for deep learning accelerator.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.
IEEE Robotics and Automation Letters, 2018

AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability.
J. Low Power Electronics, 2018

Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators.
J. Low Power Electronics, 2018

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.
SCIENCE CHINA Information Sciences, 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Lightweight Timing Channel Protection for Shared DRAM Controller.
Proceedings of the IEEE International Test Conference, 2018

Tetris: re-architecting convolutional neural network computation for machine learning accelerators.
Proceedings of the International Conference on Computer-Aided Design, 2018

A retrospective evaluation of energy-efficient object detection solutions on embedded devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Hardware Trojan in FPGA CNN Accelerator.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

RiskCap: Minimizing Effort of Error Regulation for Approximate Computing.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

XORiM: A case of in-memory bit-comparator implementation and its performance implications.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

PIMCH: Cooperative memory prefetching in processing-in-memory architecture.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.
IEEE Trans. VLSI Syst., 2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. VLSI Syst., 2017

Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.
IEEE Trans. VLSI Syst., 2017

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors.
IEEE Trans. Multi-Scale Computing Systems, 2017

Exploiting the Potential of Computation Reuse Through Approximate Computing.
IEEE Trans. Multi-Scale Computing Systems, 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Power-Utility-Driven Write Management for MLC PCM.
JETC, 2017

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.
IEICE Transactions, 2017

Flip-flop clustering based trace signal selection for post-silicon debug.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image.
Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Fault diagnosis of arbiter physical unclonable function.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR.
Proceedings of the 54th Annual Design Automation Conference, 2017

Dadu: Accelerating Inverse Kinematics for High-DOF Robots.
Proceedings of the 54th Annual Design Automation Conference, 2017

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.
Proceedings of the Computing Frontiers Conference, 2017

CNN-based object detection solutions for embedded heterogeneous multicore SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. VLSI Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.
IEEE Trans. VLSI Syst., 2016

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.
IEEE Trans. VLSI Syst., 2016

EcoUp: Towards Economical Datacenter Upgrading.
IEEE Trans. Parallel Distrib. Syst., 2016

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition.
IEEE Trans. Computers, 2016

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores.
IEEE Trans. Computers, 2016

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs.
Integration, 2016

Path constraint solving based test generation for observability-enhanced branch coverage.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.
Proceedings of the 2016 IEEE International Test Conference, 2016

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.
Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.
Proceedings of the 53rd Annual Design Automation Conference, 2016

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
Proceedings of the 53rd Annual Design Automation Conference, 2016

POSTER: Attack on Non-Linear Physical Unclonable Function.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

ACR: Enabling computation reuse for approximate computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Data Remapping for Static NUCA in Degradable Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.
IEEE Trans. VLSI Syst., 2015

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors.
IEEE Trans. VLSI Syst., 2015

An on-chip frequency programmable test clock generation and application method for small delay defect detection.
Integration, 2015

A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electronic Express, 2015

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

OPUF: Obfuscation logic based physical unclonable function.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Retraining-based timing error mitigation for hardware neural networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Impact assessment of net metering on smart home cyberattack detection.
Proceedings of the 52nd Annual Design Automation Conference, 2015

TURO: A lightweight turn-guided routing scheme for 3D NoCs.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Lightweight Timing Channel Protection for Shared Memory Controllers.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Diagnose Failures Caused by Multiple Locations at a Time.
IEEE Trans. VLSI Syst., 2014

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. VLSI Syst., 2014

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs.
IEEE Trans. VLSI Syst., 2014

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications.
IEEE Trans. VLSI Syst., 2014

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.
IEEE Trans. VLSI Syst., 2014

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications.
IEEE Trans. VLSI Syst., 2014

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor.
ACM Trans. Design Autom. Electr. Syst., 2014

A novel abstraction-guided simulation approach using posterior probabilities for verification.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Short-SET: An energy-efficient write scheme for MLC PCM.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Functional test generation guided by steady-state probabilities of abstract design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Partial-SET: Write speedup of PCM main memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SuperRange: Wide operational range power delivery design for both STV and NTV computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

On-Chip Delay Sensor for Environments with Large Temperature Fluctuations.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

An On-Line Timing Error Detection Method for Silicon Debug.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.
IEEE Trans. VLSI Syst., 2013

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.
IEEE Trans. VLSI Syst., 2013

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model.
IEEE Trans. VLSI Syst., 2013

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.
IEEE Trans. VLSI Syst., 2013

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.
J. Comput. Sci. Technol., 2013

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.
J. Comput. Sci. Technol., 2013

RSAK: Random stream attack for phase change memory in video applications.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Diagnosis and Layout Aware (DLA) scan chain stitching.
Proceedings of the 2013 IEEE International Test Conference, 2013

On predicting NBTI-induced circuit aging by isolating leakage change.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Capturing post-silicon variation by layout-aware path-delay testing.
Proceedings of the Design, Automation and Test in Europe, 2013

SmartCap: user experience-oriented power adaptation for smartphone's application processor.
Proceedings of the Design, Automation and Test in Europe, 2013

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications.
Proceedings of the Design, Automation and Test in Europe, 2013

RISO: relaxed network-on-chip isolation for cloud processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Path Constraint Solving Based Test Generation for Hard-to-Reach States.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
An energy-efficient link quality monitoring scheme for wireless networks.
Wireless Communications and Mobile Computing, 2012

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume.
IEEE Trans. VLSI Syst., 2012

A High-Precision On-Chip Path Delay Measurement Architecture.
IEEE Trans. VLSI Syst., 2012

Testable Path Selection and Grouping for Faster Than At-Speed Testing.
IEEE Trans. VLSI Syst., 2012

Statistical SDFC: A metric for evaluating test quality of small delay faults.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Off-path leakage power aware routing for SRAM-based FPGAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

In-Field Testing of NAND Flash Storage: Why and How?
Proceedings of the 21st IEEE Asian Test Symposium, 2012

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.
IEEE Trans. VLSI Syst., 2011

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects.
IEEE Trans. VLSI Syst., 2011

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation.
IEEE Trans. VLSI Syst., 2011

MicroFix: Using timing interpolation and delay sensors for power reduction.
ACM Trans. Design Autom. Electr. Syst., 2011

A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems.
IEEE Trans. Industrial Electronics, 2011

Nonidentical Linear Pulse-Coupled Oscillators Model With Application to Time Synchronization in Wireless Sensor Networks.
IEEE Trans. Industrial Electronics, 2011

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.
IEEE Trans. Computers, 2011

Capture-power-aware test data compression using selective encoding.
Integration, 2011

Statistical lifetime reliability optimization considering joint effect of process variation and aging.
Integration, 2011

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.
IEICE Transactions, 2011

A Security Mechanism For RFID With Dependable Proxy.
Intelligent Automation & Soft Computing, 2011

Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection.
Intelligent Automation & Soft Computing, 2011

Scan chain design for shift power reduction in scan-based testing.
SCIENCE CHINA Information Sciences, 2011

A unified test architecture for on-line and off-line delay fault detections.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Online timing variation tolerance for digital integrated circuits.
Proceedings of the 2011 IEEE International Test Conference, 2011

An abacus turn model for time/space-efficient reconfigurable routing.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

A greedy approach to tolerate defect cores for multimedia applications.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors.
Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

On diagnosis of multiple faults using compacted responses.
Proceedings of the Design, Automation and Test in Europe, 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
Proceedings of the Design, Automation and Test in Europe, 2011

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies.
Proceedings of the Design, Automation and Test in Europe, 2011

Cross-layer optimized placement and routing for FPGA soft error mitigation.
Proceedings of the Design, Automation and Test in Europe, 2011

Eliminating data invalidation in debugging multiple-clock chips.
Proceedings of the Design, Automation and Test in Europe, 2011

Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
Proceedings of the 48th Design Automation Conference, 2011

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A resilient on-chip router design through data path salvaging.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Passive Loss Inference in Wireless Sensor Networks Using EM Algorithm.
Wireless Sensor Network, 2010

Linear Pulse-Coupled Oscillators Model¬ - A New Approach for Time Synchronization in Wireless Sensor Networks.
Wireless Sensor Network, 2010

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.
IEEE Trans. VLSI Syst., 2010

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
Journal of Systems Architecture - Embedded Systems Design, 2010

A Novel Post-Silicon Debug Mechanism Based on Suspect Window.
IEICE Transactions, 2010

Testable Critical Path Selection Considering Process Variation.
IEICE Transactions, 2010

Fast path selection for testing of small delay defects considering path correlations.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Improving complex distributed software system availability through information hiding.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
Proceedings of the 2011 IEEE International Test Conference, 2010

On generation of a universal path candidate set containing testable long paths.
Proceedings of the 2011 IEEE International Test Conference, 2010

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.
Proceedings of the Design, Automation and Test in Europe, 2010

An abstraction-guided simulation approach using Markov models for microprocessor verification.
Proceedings of the Design, Automation and Test in Europe, 2010

Diagnosis of multiple arbitrary faults with mask and reinforcement effect.
Proceedings of the Design, Automation and Test in Europe, 2010

An on-chip clock generation scheme for faster-than-at-speed delay testing.
Proceedings of the Design, Automation and Test in Europe, 2010

IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults.
Proceedings of the Design, Automation and Test in Europe, 2010

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

Software-Based Self-Testing of Processors Using Expanded Instructions.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Graph partition based path selection for testing of small delay defects.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.
IEEE Trans. VLSI Syst., 2009

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip.
J. Comput. Sci. Technol., 2009

Preface.
J. Comput. Sci. Technol., 2009

A sensor network performance inference algorithm based on passive measurement.
Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009

Automatic Selection of Internal Observation Signals for Design Verification.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A New Post-Silicon Debug Approach Based on Suspect Window.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact of Hazards on Pattern Selection for Small Delay Defects.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A unified online Fault Detection scheme via checking of Stability Violation.
Proceedings of the Design, Automation and Test in Europe, 2009

A Low Overhead On-Chip Path Delay Measurement Circuit.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN.
Signal Processing Systems, 2008

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.
J. Comput. Sci. Technol., 2008

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission.
IEICE Transactions, 2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Multiple Coupling Effects Oriented Path Delay Test Generation.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

On capture power-aware test data compression for scan-based testing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Static Crosstalk Noise Analysis with Transition Map.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Case Study on At-Speed Testing for a Gigahertz Microprocessor.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Adaptive Diagnostic Pattern Generation for Scan Chains.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Scan-Based Delay Test Method for Reduction of Overtesting.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
Proceedings of the Design, Automation and Test in Europe, 2008

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.
Proceedings of the Design, Automation and Test in Europe, 2008

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

On reducing both shift and capture power for scan-based testing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robust test generation for power supply noise induced path delay faults.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst., 2007

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.
J. Comput. Sci. Technol., 2007

Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks.
International Journal of Information Technology and Decision Making, 2007

The design-for-testability features of a general purpose microprocessor.
Proceedings of the 2007 IEEE International Test Conference, 2007

Bug analysis and corresponding error models in real designs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Routing Algorithm for Random Error Tolerance in Network-on-Chip.
Proceedings of the Human-Computer Interaction. HCI Applications and Services, 2007

2006
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.
IEEE Trans. Instrumentation and Measurement, 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions, 2006

Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification.
J. Electronic Testing, 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences, 2006

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

An on-chip combinational decompressor for reducing test data volume.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime.
Proceedings of the Computational Science, 2006

Fast Packet Classification using Group Bit Vector.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks.
Proceedings of the Advanced Web and Network Technologies, and Applications, 2006

A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005
An innovative free memory design for network processors in home network gateway.
IEEE Trans. Consumer Electronics, 2005

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage.
J. Comput. Sci. Technol., 2005

Formal Verification Techniques Based on Boolean Satisfiability Problem.
J. Comput. Sci. Technol., 2005

Perface.
J. Comput. Sci. Technol., 2005

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions, 2005

Selection of Crosstalk-Induced Faults in Enhanced Delay Test.
J. Electronic Testing, 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Using MUXs Network to Hide Bunches of Scan Chains.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Validation analysis and test flow optimization of VLSI chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Deterministic and low power BIST based on scan slice overlapping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Non-robust Test Generation for Crosstalk-Induced Delay Faults.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A State Machine for Detecting C/C++ Memory Faults.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

The Automatic Generation of Basis Set of Path for Path Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Vector extraction for average total power estimation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design of an efficient memory subsystem for network processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Leakage Current Estimation of CMOS Circuit with Stack Effect.
J. Comput. Sci. Technol., 2004

Conference Reports.
IEEE Design & Test of Computers, 2004

A maximum total leakage current estimation method.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

Circuit-Width Based Heuristic for Boolean Reasoning.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Pair Balance-Based Test Scheduling for SOCs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A Novel RT-Level Behavioral Description Based ATPG Method.
J. Comput. Sci. Technol., 2003

Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

SAT-Based Algorithm of Verification for Port Order Fault.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Delay Test Pattern Generation Considering Crosstalk-Induced Effects.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Design Error Diagnosis Based on Verification Techniques.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

An Expression's Single Fault Model and the Testing Methods.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications.
Science in China Series F: Information Sciences, 2002

Test Power Optimization Techniques for CMOS Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
A Loop-Based Apparatus for At-Speed Self-Testing.
J. Comput. Sci. Technol., 2001

Reducing Power Dissipation during At-Speed Test Application.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An Approach to RTL Fault Extraction and Test Generation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Exploiting Deterministic TPG for Path Delay Testing.
J. Comput. Sci. Technol., 2000

High Level Synthesis for Loop-Based BIST.
J. Comput. Sci. Technol., 2000

LFSR-Based Deterministic TPG for Two-Pattern Testing.
J. Electronic Testing, 2000

Strong self-testability for data paths high-level synthesis.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
An approach to behavioral synthesis for loop-based BIST.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Exploiting Test Resource Optimization in Data Path Synthesis for BIST.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Data Path Synthesis for BIST with Low Area Overhead.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
High-Level BIST Synthesis for Delay Testing.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Exploiting BIST Approach for Two-Pattern Testing.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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