Haoxing Ren

Chenhui Deng

CoRR, June, 2025

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems.

[BibT_eX]

[DOI]

CoRR, June, 2025

PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification.

[BibT_eX]

[DOI]

CoRR, June, 2025

HeuriGym: An Agentic Benchmark for LLM-Crafted Heuristics in Combinatorial Optimization.

[BibT_eX]

[DOI]

CoRR, June, 2025

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation.

[BibT_eX]

[DOI]

CoRR, June, 2025

LiDAR 2.0: Hierarchical Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits.

[BibT_eX]

[DOI]

CoRR, May, 2025

JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation.

[BibT_eX]

[DOI]

CoRR, May, 2025

Deep Physics Prior for First Order Inverse Optimization.

[BibT_eX]

[DOI]

Kamyar Azizzadenesheli

CoRR, April, 2025

Automated Routing-Informed Placement for Large-Scale Photonic Integrated Circuits.

[BibT_eX]

[DOI]

CoRR, April, 2025

Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph.

[BibT_eX]

[DOI]

CoRR, April, 2025

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design.

[BibT_eX]

[DOI]

CoRR, April, 2025

Learning Library Cell Representations in Vector Space.

[BibT_eX]

[DOI]

CoRR, March, 2025

AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL.

[BibT_eX]

[DOI]

CoRR, March, 2025

Cypress: VLSI-Inspired PCB Placement with GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

GPU-Accelerated Inverse Lithography Towards High Quality Curvy Mask Generation.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes.

[BibT_eX]

[DOI]

Ravikishore Gandikota

Proceedings of the 2025 International Symposium on Physical Design, 2025

Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

GOALPlace: Begin with the End in Mind.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Conference on Learning Representations, 2025

SimPart: A Simple Yet Effective Replication-Aided Partitioning Algorithm for Logic Simulation on GPU.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2025: Parallel Processing, 2025

ChipVQA: Benchmarking Visual Language Models for Chip Design.

[BibT_eX]

[DOI]

Qijing Huang

Proceedings of the Design, Automation & Test in Europe Conference, 2025

FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

BOSON<sup>-1</sup>: Understanding and Enabling Physically-Robust Photonic Inverse Design with Adaptive Variation-Aware Subspace Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.

[BibT_eX]

[DOI]

Chia-Tung Ho

Proceedings of the AAAI-25, Sponsored by the Association for the Advancement of Artificial Intelligence, February 25, 2025

Intelligent OPC Engineer Assistant for Semiconductor Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the AAAI-25, Sponsored by the Association for the Advancement of Artificial Intelligence, February 25, 2025

2024

DAG-Aware Synthesis Orchestration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2024

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation.

[BibT_eX]

[DOI]

Chenhui Deng

Yunsheng Bai

CoRR, 2024

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks.

[BibT_eX]

[DOI]

CoRR, 2024

Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning.

[BibT_eX]

[DOI]

Yun-Da Tsai

CoRR, 2024

Large Language Model (LLM) for Standard Cell Layout Design Optimization.

[BibT_eX]

[DOI]

Chia-Tung Ho

CoRR, 2024

Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance.

[BibT_eX]

[DOI]

CoRR, 2024

Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent.

[BibT_eX]

[DOI]

Anthony Agnesina

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs.

[BibT_eX]

[DOI]

Christopher Batten

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Learning to Compare Hardware Designs for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Challenges for Automating PCB Layout.

[BibT_eX]

[DOI]

Wen-Hao Liu

Anthony Agnesina

Haoxing Mark Ren

Proceedings of the 2024 International Symposium on Physical Design, 2024

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner.

[BibT_eX]

[DOI]

Rongjian Liang

Anthony Agnesina

Proceedings of the 2024 International Symposium on Physical Design, 2024

GPU/ML-Enhanced Large Scale Global Routing Contest.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

ILILT: Implicit Learning of Inverse Lithography Technologies.

[BibT_eX]

[DOI]

Proceedings of the Forty-first International Conference on Machine Learning, 2024

Invited Paper: LLM4HWDesign Contest: Constructing a Comprehensive Dataset for LLM-Assisted Hardware Code Generation with Community Efforts.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing Using ML Techniques and GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Differentiable Edge-based OPC.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model.

[BibT_eX]

[DOI]

Yunda Tsai

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

DGR: Differentiable Global Router.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Introduction to the Special Issue on Machine Learning for CAD/EDA.

[BibT_eX]

[DOI]

Yibo Lin

Avi Ziv

ACM Trans. Design Autom. Electr. Syst., March, 2023

Machine Learning and Algorithms: Let Us Team Up for EDA.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.

[BibT_eX]

[DOI]

Yun-Da Tsai

CoRR, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.

[BibT_eX]

[DOI]

CoRR, 2023

VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

[BibT_eX]

[DOI]

CoRR, 2023

DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

AutoDMP: Automated DREAMPlace-based Macro Placement.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Enabling Scalable AI Computational Lithography with Physics-Inspired Models.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

BufFormer: A Generative ML Framework for Scalable Buffering.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design.

[BibT_eX]

[DOI]

Saumyadip Mukhopadhyay

CoRR, 2022

Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training.

[BibT_eX]

[DOI]

Zongyi Li

Kumara Sastry

Saumyadip Mukhopadhyay

CoRR, 2022

Placement Optimization via PPA-Directed Graph Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Embracing Machine Learning in EDA.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus.

[BibT_eX]

[DOI]

Proceedings of the 51st International Conference on Parallel Processing, 2022

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TransSizer: A Novel Transformer-Based Fast Gate Sizer.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TAG: Learning Circuit Spatial Embedding from Layouts.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

GATSPI: GPU accelerated gate-level simulation for power improvement.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generic lithography modeling with dual-band optics-inspired neural networks.

[BibT_eX]

[DOI]

Zongyi Li

Kumara Sastry

Saumyadip Mukhopadhyay

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generative self-supervised learning for gate sizing: invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.

[BibT_eX]

[DOI]

Matthew Fojtik

CoRR, 2021

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.

[BibT_eX]

[DOI]

Steve Dai

Alicia Klinefelter

Rangharajan Venkatesan

Ben Keller

CoRR, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.

[BibT_eX]

[DOI]

Steve Dai

Rangharajan Venkatesan

CoRR, 2021

Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.

[BibT_eX]

[DOI]

Matthew Fojtik

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes.

[BibT_eX]

[DOI]

Matthew Fojtik

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Chip Design With Machine Learning.

[BibT_eX]

[DOI]

Rangharajan Venkatesan

Bryan Catanzaro

William J. Dally

IEEE Micro, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.

[BibT_eX]

[DOI]

CoRR, 2020

ML for CAD - Where is the Treasure Hiding?

[BibT_eX]

[DOI]

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.

[BibT_eX]

[DOI]

Erick Carvajal Barboza

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Toward Intelligent Physical Design: Deep Learning and GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

PRIMAL: Power Inference using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.

[BibT_eX]

[DOI]

Karthikeyan Natarajan

Bei Yu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

RouteNet: routability prediction for mixed-size designs using convolutional neural network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2014

A brief introduction on contemporary High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013

Network flow based datapath bit slicing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Design methodology for the IBM POWER7 microprocessor.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2011

2010

Logical and physical restructuring of fan-in trees.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

History-based VLSI legalization using network flow.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Low cost test point insertion without using extra registers for high performance design.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

DeltaSyn: An efficient logic difference optimizer for ECO synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Timing-Driven Placement.

[BibT_eX]

[DOI]

David Z. Pan

Bill Halpin

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Placement-Driven Synthesis Design Closure Tool.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007

Diffusion-Based Placement Migration With Application on Legalization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.

[BibT_eX]

[DOI]

Charles J. Alpert

Shrirang K. Karandikar

Proc. IEEE, 2007

The nuts and bolts of physical synthesis.

[BibT_eX]

[DOI]

Charles J. Alpert

Shrirang K. Karandikar

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005

Sensitivity guided net weighting for placement-driven synthesis.

[BibT_eX]

[DOI]

David Zhigang Pan

David S. Kung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Computational geometry based placement migration.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

True crosstalk aware incremental placement with noise map.

[BibT_eX]

[DOI]