Francesco Conti

According to our database1, Francesco Conti authored at least 55 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node.
IEEE Trans. Circuits Syst., 2020

Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor.
IEEE Trans. Biomed. Circuits Syst., 2020

Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes.
CoRR, 2020

Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020

DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs.
CoRR, 2020

Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node.
CoRR, 2020

Technical Report: NEMO DNN Quantization for Deployment Model.
CoRR, 2020

Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Enabling mixed-precision quantized neural networks in extreme-edge devices.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones.
IEEE Internet Things J., 2019

PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors.
CoRR, 2019

Optimally Scheduling CNN Convolutions for Efficient Memory Access.
CoRR, 2019

PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs.
Proceedings of the 15th International Conference on Distributed Computing in Sensor Systems, 2019

DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Ultra Low Power Deep-Learning-powered Autonomous Nano Drones.
CoRR, 2018

Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project.
Proceedings of the 30th International Conference on Microelectronics, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

Chipmunk: A systolically scalable 0.9 mm<sup>2</sup>, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Thermal image-based CNN's for ultra-low power people recognition.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Accelerated Visual Context Classification on a Low-Power Smartwatch.
IEEE Trans. Hum. Mach. Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017

Chipmunk: A Systolically Scalable 0.9 mm<sup>2</sup>, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference.
CoRR, 2017

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Heterogeneous Architectures For Parallel Acceleration.
PhD thesis, 2016

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores.
J. Signal Process. Syst., 2016

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst., 2016

On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocess. Microsystems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Online process transformation for polyhedral process networks in shared-memory MPSoCs.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014

He-P2012: Architectural heterogeneity exploration on a scalable many-core platform.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013


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