Rajesh K. Gupta

According to our database1, Rajesh K. Gupta authored at least 285 papers between 1990 and 2020.

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Bibliography

2020
Local Binary Pattern Networks.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2020

2019
Variability Expeditions: A Retrospective.
IEEE Des. Test, 2019

ACES - Automatic Configuration of Energy Harvesting Sensors with Reinforcement Learning.
CoRR, 2019

Associative Convolutional Layers.
CoRR, 2019

A Wearable, Extensible, Open-Source Platform for Hearing Healthcare Research.
IEEE Access, 2019

Interactive Building Metadata Normalization.
Proceedings of the 6th ACM International Conference on Systems for Energy-Efficient Buildings, 2019

Who can Access What, and When?: Understanding Minimal Access Requirements of Building Applications.
Proceedings of the 6th ACM International Conference on Systems for Energy-Efficient Buildings, 2019

Beyond a House of Sticks: Formalizing Metadata Tags with Brick.
Proceedings of the 6th ACM International Conference on Systems for Energy-Efficient Buildings, 2019

Serving deep neural networks at the cloud edge for vision applications on mobile platforms.
Proceedings of the 10th ACM Multimedia Systems Conference, 2019

New models and methods for programming cyber-physical systems (keynote).
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Real Time Principal Component Analysis.
Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Multi-tenant mobile offloading systems for real-time computer vision applications.
Proceedings of the 20th International Conference on Distributed Computing and Networking, 2019

Towards verified programming of embedded devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accurate Estimation of Program Error Rate for Timing-Speculative Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers, 2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018

Local Binary Pattern Networks.
CoRR, 2018

SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Reliability-Aware Data Placement for Heterogeneous Memory Architecture.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Embedded software for robotics: challenges and future directions: special session.
Proceedings of the International Conference on Embedded Software, 2018

Energy-efficient neural networks using approximate computation reuse.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

LEMAX: learning-based energy consumption minimization in approximate computing with quality guarantee.
Proceedings of the 55th Annual Design Automation Conference, 2018

Mitigating Multi-tenant Interference in Continuous Mobile Offloading.
Proceedings of the Cloud Computing - CLOUD 2018, 2018

A Wearable Platform for Research in Augmented Hearing.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Sampled-Time-Domain Analysis of a Digitally Implemented Current Controlled Inverter.
IEEE Trans. Ind. Electron., 2017

Go-realtime: a lightweight framework for multiprocessor real-time system in user space.
SIGBED Rev., 2017

ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

SLoT: A supervised learning model to predict dynamic timing errors of functional units.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Combining structural and timing errors in overclocked inexact speculative adders.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.
Proceedings of the 54th Annual Design Automation Conference, 2017

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017

Mitigating multi-tenant interference on mobile offloading servers: poster abstract.
Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, 2017

QoS-Aware Scheduling of Heterogeneous Servers for Inference in Deep Neural Networks.
Proceedings of the 2017 ACM on Conference on Information and Knowledge Management, 2017

Exploiting Synchrony in Replicated State Machines.
Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017

2016
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software.
Proceedings of the IEEE, 2016

Associative Memristive Memory for Approximate Computing in GPUs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

CIRCA-GPUs: Increasing Instruction Reuse Through Inexact Computing in GP-GPUs.
IEEE Des. Test, 2016

Quiver: Using Control Perturbations to Increase the Observability of Sensor Data in Smart Buildings.
CoRR, 2016

Portable Queries Using the Brick Schema for Building Applications: Demo Abstract.
Proceedings of the 3rd ACM International Conference on Systems for Energy-Efficient Built Environments, 2016

Reliability and Performance Trade-off Study of Heterogeneous Memories.
Proceedings of the Second International Symposium on Memory Systems, 2016

WILD: A workload-based learning model to predict dynamic delay of functional units.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Strategies for optimal operating point selection in timing speculative processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Resistive Bloom filters: From approximate membership to approximate computing with bounded errors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Aging-Aware Compilation for GP-GPUs.
ACM Trans. Archit. Code Optim., 2015

NSF expedition on variability-aware software: Recent results and contributions.
it Inf. Technol., 2015

HVACMeter: Apportionment of HVAC Power to Thermal Zones and Air Handler Units.
CoRR, 2015

Supervised learning based model for predicting variability-induced timing errors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Approximate associative memristive memory for energy-efficient GPUs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Models, abstractions, and architectures: the missing links in cyber-physical systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability.
IEEE Trans. Computers, 2014

Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Data driven investigation of faults in HVAC systems with model, cluster and compare (MCC).
Proceedings of the 1st ACM Conference on Embedded Systems for Energy-Efficient Buildings, 2014

Temporal memoization for energy-efficient timing error recovery in GPGPUs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Timing analysis of erroneous systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Workload Shaping to Mitigate Variability in Renewable Power Use by Data Centers.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

2013
Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Underdesigned and Opportunistic Computing in Presence of Hardware Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Introductions to special issue on ESWEEK 2011.
Design Autom. for Emb. Sys., 2013

From ARIES to MARS: transaction support for next-generation, solid-state drives.
Proceedings of the ACM SIGOPS 24th Symposium on Operating Systems Principles, 2013

Sentinel: occupancy based HVAC actuation using existing WiFi infrastructure within commercial buildings.
Proceedings of the 11th ACM Conference on Embedded Network Sensor Systems, 2013

Energy-optimized dynamic deferral of workload for capacity provisioning in data centers.
Proceedings of the International Green Computing Conference, 2013

Minerva: Accelerating Data Analysis in Next-Generation SSDs.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Variation-tolerant OpenMP tasking on tightly-coupled processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging.
Proceedings of the Design, Automation and Test in Europe, 2013

Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity.
Proceedings of the Design, Automation and Test in Europe, 2013

Aging-aware compiler-directed VLIW assignment for GPGPU architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

ARGO: Aging-aware GPGPU register file allocation.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Path Consolidation for Dynamic Right-Sizing of Data Center Networks.
Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013

2012
Energy-efficient deadline scheduling for heterogeneous systems.
J. Parallel Distributed Comput., 2012

Message From the Steering Committee.
IEEE Des. Test Comput., 2012

Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines.
Proceedings of the 25th International Conference on VLSI Design, 2012

Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing.
Proceedings of the 25th International Conference on VLSI Design, 2012

BuildingDepot: an extensible and distributed architecture for building data storage, access and sharing.
Proceedings of the BuildSys '12 Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, 2012

Verifying GPU kernels by test amplification.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012

Accurate Characterization of the Variability in Power Consumption in Modern Mobile Processors.
Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Energy Efficient Geographical Load Balancing via Dynamic Deferral of Workload.
Proceedings of the 2012 IEEE Fifth International Conference on Cloud Computing, 2012

2011
Path Planning of Data Mules in Sensor Networks.
ACM Trans. Sens. Networks, 2011

Integrating Embedded Computing Systems Into High School and Early Undergraduate Education.
IEEE Trans. Educ., 2011

Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture.
IEEE Des. Test Comput., 2011

Dynamic Deferral of Workload for Capacity Provisioning in Data Centers
CoRR, 2011

Managing plug-loads for demand response within buildings.
Proceedings of the BuildSys 2011, 2011

Duty-cycling buildings aggressively: The next frontier in HVAC control.
Proceedings of the 10th International Conference on Information Processing in Sensor Networks, 2011

Sensor localization with deterministic accuracy guarantee.
Proceedings of the INFOCOM 2011. 30th IEEE International Conference on Computer Communications, 2011

Programming Support for Distributed Optimization and Control in Cyber-Physical Systems.
Proceedings of the 2011 IEEE/ACM International Conference on Cyber-Physical Systems, 2011

Onyx: A Prototype Phase Change Memory Storage Array.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Storage and File Systems, 2011

Clock Synchronization with Deterministic Accuracy Guarantee.
Proceedings of the Wireless Sensor Networks - 8th European Conference, 2011

Understanding the role of buildings in a smart microgrid.
Proceedings of the Design, Automation and Test in Europe, 2011

Underdesigned and Opportunistic Computing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

High-Level Verification - Methods and Tools for Verification of System-Level Designs.
Springer, ISBN: 978-1-4419-9358-8, 2011

2010
Speed control and scheduling of data mules in sensor networks.
ACM Trans. Sens. Networks, 2010

Optimal Speed Control of Mobile Node for Data Collection in Sensor Networks.
IEEE Trans. Mob. Comput., 2010

Translation Validation of High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

SleepServer: A Software-Only Approach for Reducing the Energy Consumption of PCs within Enterprise Environments.
Proceedings of the 2010 USENIX Annual Technical Conference, 2010

Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing.
Proceedings of the Conference on High Performance Computing Networking, 2010

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks.
ACM Trans. Design Autom. Electr. Syst., 2009

Processor Speed Control With Thermal Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

High-Level Verification.
IPSJ Trans. System LSI Design Methodology, 2009

Cycle accurate transaction-driven simulation with multiple processor simulators.
IEICE Electron. Express, 2009

Softspeak: Making VoIP Play Well in Existing 802.11 Deployments.
Proceedings of the 6th USENIX Symposium on Networked Systems Design and Implementation, 2009

Somniloquy: Augmenting Network Interfaces to Reduce PC Energy Usage.
Proceedings of the 6th USENIX Symposium on Networked Systems Design and Implementation, 2009

Improving the speed and scalability of distributed simulations of sensor networks.
Proceedings of the 8th International Conference on Information Processing in Sensor Networks, 2009

Optimizing Energy-Latency Trade-Off in Sensor Networks with Controlled Mobility.
Proceedings of the INFOCOM 2009. 28th IEEE International Conference on Computer Communications, 2009

LazySync: A New Synchronization Scheme for Distributed Simulation of Sensor Networks.
Proceedings of the Distributed Computing in Sensor Systems, 2009

2008
Programming models for sensor networks: A survey.
ACM Trans. Sens. Networks, 2008

Advances in ESL Design.
IEEE Des. Test Comput., 2008

SwitchR: Reducing system power consumption in a multi-client, multi-radio environment.
Proceedings of the 12th IEEE International Symposium on Wearable Computers (ISWC 2008), September 28, 2008

Improving the Data Delivery Latency in Sensor Networks with Controlled Mobility.
Proceedings of the Distributed Computing in Sensor Systems, 2008

Improved Distributed Simulation of Sensor Networks Based on Sensor Node Sleep Time.
Proceedings of the Distributed Computing in Sensor Systems, 2008

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

Partial order reduction for scalable testing of systemC TLM designs.
Proceedings of the 45th Design Automation Conference, 2008

Validating High-Level Synthesis.
Proceedings of the Computer Aided Verification, 20th International Conference, 2008

2007
Algorithms for power savings.
ACM Trans. Algorithms, 2007

An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Wireless wakeups revisited: energy management for voip over wi-fi smartphones.
Proceedings of the 5th International Conference on Mobile Systems, 2007

Automated refinement checking of concurrent systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Reactivity in SystemC Transaction-Level Models.
Proceedings of the Hardware and Software: Verification and Testing, 2007

CATS: cycle accurate transaction-driven simulation with multiple processor simulators.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Temperature-aware processor frequency assignment for MPSoCs using convex optimization.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Energy efficient watermarking on mobile devices using proxy-based partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Frequency-domain characterization of sliding mode control of an inverter used in DSTATCOM application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Energy-aware task scheduling with task synchronization for embedded real-time systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Optimized Slowdown in Real-Time Task Systems.
IEEE Trans. Computers, 2006

A Verification Approach for GALS Integration of Synchronous Components.
Electron. Notes Theor. Comput. Sci., 2006

<i>CoolSpots</i>: reducing the power consumption of wireless mobile devices with multiple radio interfaces.
Proceedings of the 4th International Conference on Mobile Systems, 2006

Programming models and languages for SoC-implemented architectures.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Compositional interaction specifications for SystemC.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Parallel co-simulation using virtual synchronization with redundant host execution.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Phase guided sampling for efficient parallel application simulation.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Declarative Resource Naming for Macroprogramming Wireless Networks of Embedded Systems.
Proceedings of the Algorithmic Aspects of Wireless Sensor Networks, 2006

2005
Design Issues for Networked Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Energy-aware wireless systems with adaptive power-fidelity tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

An overview of the competitive and adversarial approaches to designing dynamic power management strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.
IEEE Trans. Computers, 2005

A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking.
Int. J. Parallel Program., 2005

Using probabilistic model checking for dynamic power management.
Formal Aspects Comput., 2005

Going 3D: Silicon and D&T.
IEEE Des. Test Comput., 2005

On-chip networks.
IEEE Des. Test Comput., 2005

Nanotechnology: Where science of the small meets math of the large.
IEEE Des. Test Comput., 2005

The other face of design for manufacturability.
IEEE Des. Test Comput., 2005

FPGA-enabled computing architectures.
IEEE Des. Test Comput., 2005

Global competitiveness, outsourcing, and education in the semiconductor industry.
IEEE Des. Test Comput., 2005

Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Improving SystemC simulation through Petri net reductions.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems.
Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS 2005), 2005

Dynamic slack reclamation with procrastination scheduling in real-time embedded systems.
Proceedings of the 42nd Design Automation Conference, 2005

Dynamic phase analysis for cycle-close trace generation.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Dynamic power management using on demand paging for networked embedded systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An Introductory Survey of Networked Embedded Systems.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Coordinated parallelizing compiler optimizations and high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 2004

Guest editorial: Special issue on networked embedded systems.
ACM Trans. Embed. Comput. Syst., 2004

Using global code motions to improve the quality of results for high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Formal Refinement Checking in a System-level Design Methodology.
Fundam. Informaticae, 2004

Verification synergies.
IEEE Des. Test Comput., 2004

Silicon for embedded multimedia processing.
IEEE Des. Test Comput., 2004

From the EIC: The next EDA challenge - Design for manufacturability.
IEEE Des. Test Comput., 2004

From the EIC: Past successes, future challenges.
IEEE Des. Test Comput., 2004

From the Editor in Chief: Predictability in Design and Manufacturing.
IEEE Des. Test Comput., 2004

Procrastination scheduling in fixed priority real-time systems.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 2004

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.
Proceedings of the 2004 Design, 2004

Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2004 Design, 2004

Energy-Aware System Design for Wireless Multimedia.
Proceedings of the 2004 Design, 2004

Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices.
Proceedings of the 41th Design Automation Conference, 2004

Leakage aware dynamic voltage scaling for real-time embedded systems.
Proceedings of the 41th Design Automation Conference, 2004

Reactive Framework for Resource Aware Distributed Computing.
Proceedings of the Advances in Computer Science, 2004

A Behavioral Type Inference System for Compositional System-on-Chip Design.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

Energy-Aware Adaptations for End-to-End Videostreaming to Mobile Handheld Devices.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Online strategies for dynamic power management in systems with multiple power-saving states.
ACM Trans. Embed. Comput. Syst., 2003

BALBOA: a component-based design environment for system models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

From the EIC: The changing face of IC design and its industry.
IEEE Des. Test Comput., 2003

At-Speed Testing: A Shared Red Brick between Design and Test.
IEEE Des. Test Comput., 2003

From the Editor in Chief: Addressing Problems of the Large.
IEEE Des. Test Comput., 2003

From the Editor in Chief: A "Powerful" Issue!
IEEE Des. Test Comput., 2003

From the Editor in Chief: Full Circle?
IEEE Des. Test Comput., 2003

From the Editor in Chief: Twenty years!
IEEE Des. Test Comput., 2003

Driving Research in System-Chip Design Technology.
Computer, 2003

High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

FORGE: A Framework for Optimization of Distributed Embedded Systems Software.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Interface Synthesis using Memory Mapping for an FPGA Platform.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Formal Methods for Dynamic Power Management.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Polychrony for Refinement-Based Design.
Proceedings of the 2003 Design, 2003

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs.
Proceedings of the 2003 Design, 2003

Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated.
Proceedings of the 2003 Design, 2003

A survey of techniques for energy efficient on-chip communication.
Proceedings of the 40th Design Automation Conference, 2003

Formal verification - prove it or pitch it.
Proceedings of the 40th Design Automation Conference, 2003

Typing abstractions and management in a component framework.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Polychrony for Formal Refinement-Checking in a System-Level Design Methodology.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

2002
Synthesis and Optimization of Combinational Interface Circuits.
J. VLSI Signal Process., 2002

An analysis of system level power management algorithms and theireffects on latency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

EIC Message: The Neglected Community.
IEEE Des. Test Comput., 2002

Sustaining an Industry Obsession.
IEEE Des. Test Comput., 2002

A Methodology for Synthesis of Data Path Circuitse.
IEEE Des. Test Comput., 2002

Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Efficient Simulation of Synthesis-Oriented System Level Designs.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Formal analysis and validation of continuous-time Markov chain based system level power management strategies.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Using Aspect-GAMMA in the design of embedded systems.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Structured Component Composition Frameworks for Embedded System Design.
Proceedings of the High Performance Computing, 2002

Power Savings in Embedded Processors through Decode Filer Cache.
Proceedings of the 2002 Design, 2002

Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation.
Proceedings of the 2002 Design, 2002

Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States.
Proceedings of the 2002 Design, 2002

An Environment for Dynamic Component Composition for Efficient Co-Design .
Proceedings of the 2002 Design, 2002

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints.
Proceedings of the 2002 Design, 2002

Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Guest editorial reconfigurable and adaptive VLSI systems.
IEEE Trans. Very Large Scale Integr. Syst., 2001

New Design Paradigms: What Needs to be Standardized?.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Conditional speculation and its effects on performance and area for high-level snthesis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Interoperability as a design issue in C++ based modeling environments.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A model checking approach to evaluating system level dynamic power management policies for embedded systems.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Speculation Techniques for High Level Synthesis of Control Intensive Designs.
Proceedings of the 38th Design Automation Conference, 2001

Panel: The Next HDL: If C++ is the Answer, What was the Question?
Proceedings of the 38th Design Automation Conference, 2001

2000
HDL presynthesis optimizations using a tabular model.
IEEE Trans. Very Large Scale Integr. Syst., 2000

YAML: A Tool for Hardware Design Visualization and Capture.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Compiler-Directed Cache Assist Adaptivity.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Compiler-Directed Cache Line Size Adaptivity.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

Interfacing Hardware and Software Using C++ Class Libraries.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Latency Effects of System Level Power Management Algorithms.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

System Level Online Power Management Algorithms.
Proceedings of the 2000 Design, 2000

Analysis of High-Level Address Code Transformations for Programmable Processors.
Proceedings of the 2000 Design, 2000

Design and implementation of a hierarchical exception handling extension to systemC.
Proceedings of the 2000 International Conference on Compilers, 2000

Timing driven co-design of networked embedded systems.
Proceedings of ASP-DAC 2000, 2000

1999
ASIC Design.
Proceedings of the VLSI Handbook., 1999

Extraction of functional regularity in datapath circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Adapting cache line size to application behavior.
Proceedings of the 13th international conference on Supercomputing, 1999

Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems.
Proceedings of the 36th Conference on Design Automation, 1999

Timing-driven HW/SW codesign based on task structuring and process timing simulation.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Rate analysis for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 1998

A timing-driven design and validation methodology for embedded real-time systems.
ACM Trans. Design Autom. Electr. Syst., 1998

Faster maximum and minimum mean cycle algorithms for system-performance analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A general approach for regularity extraction in datapath circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions.
Proceedings of the 1998 Design, 1998

Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems.
Proceedings of the 35th Conference on Design Automation, 1998

HDL code restructuring using timed decision tables.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
Specification and analysis of timing constraints for embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Implications of VHDL timing models on simulation and software synthesis.
J. Syst. Archit., 1997

Constrained software synthesis for embedded applications.
J. Syst. Archit., 1997

Design and Test of Core-Based Systems on Chips.
IEEE Des. Test Comput., 1997

Introducing Core-Based System Design.
IEEE Des. Test Comput., 1997

Using a Programming Language for Digital System Design.
IEEE Des. Test Comput., 1997

Editorial: Special Issue on Hardware/Software Partitioning.
Design Autom. for Emb. Sys., 1997

Curricular integration for next generation in microsystem design education.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

Architectural Adaptation for Application-Specific Locality Optimization.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Decomposition of timed decision tables and its use in presynthesis optimizations.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Design technology for building wireless systems (tutorial).
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

RATAN: A tool for rate analysis and rate constraint debugging for embedded systems.
Proceedings of the European Design and Test Conference, 1997

An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment.
Proceedings of the 34st Conference on Design Automation, 1997

Limited Exception Modeling and Its Use in Presynthesis Optimizations.
Proceedings of the 34st Conference on Design Automation, 1997

Data-Flow Assisted Behavioral Partitioning for Embedded Systems.
Proceedings of the 34st Conference on Design Automation, 1997

A procedure for software synthesis from VHDL models.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Design planning for high-performance ASICs.
IBM J. Res. Dev., 1996

A co-synthesis approach to embedded system design automation.
Design Autom. for Emb. Sys., 1996

Hardware Software Co-Design of Embedded Systems.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Opportunities and pitfalls in HDL-based system design.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

An algorithm for synthesis of system-level interface circuits.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Operation Serializability for Embedded Systems.
Proceedings of the 1996 European Design and Test Conference, 1996

HDL Optimization Using Timed Decision Tables.
Proceedings of the 33st Conference on Design Automation, 1996

Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems.
Proceedings of the 33st Conference on Design Automation, 1996

A framework for interactive analysis of timing constraints in embedded systems.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1994
Program Implementation Schemes for Hardware-Software Systems.
Computer, 1994

Constrained software generation for hardware-software systems.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Hardware-Software Cosynthesis for Digital Systems.
IEEE Des. Test Comput., 1993

1992
Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components.
Proceedings of the 29th Design Automation Conference, 1992

1990
Partitioning of Functional Models of Synchronous Digital Systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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