Jiang Hu

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Enhancing Datacenter Resource Management through Temporal Logic Constraints.

[BibT_eX]

[DOI]

Dilma Da Silva

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Front-end-of-line attacks in split manufacturing.

[BibT_eX]

[DOI]

Yujie Wang

Tri Cao

Jeyavijayan Rajendran

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.

[BibT_eX]

[DOI]

Jeyavijayan Rajendran

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits.

[BibT_eX]

[DOI]

Deepashree Sengupta

Farhana Sharmin Snigdha

Proceedings of the 54th Annual Design Automation Conference, 2017

A quantifiable approach to approximate computing: special session.

[BibT_eX]

[DOI]

Chaofan Li

Deepashree Sengupta

Farhana Sharmin Snigdha

Wenbin Xu

Proceedings of the 2017 International Conference on Compilers, 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

Routing perturbation for enhanced security in split manufacturing.

[BibT_eX]

[DOI]

Yujie Wang

Pu Chen

Jeyavijayan (JV) Rajendran

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Proximity Optimization for Adaptive Circuit Design.

[BibT_eX]

[DOI]

Ang Lu

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Control synthesis and delay sensor deployment for efficient ASV designs.

[BibT_eX]

[DOI]

Chaofan Li

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

The cat and mouse in split manufacturing.

[BibT_eX]

[DOI]

Yujie Wang

Pu Chen

Jeyavijayan Rajendran

Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal design of JPEG hardware under the approximate computing paradigm.

[BibT_eX]

[DOI]

Farhana Sharmin Snigdha

Deepashree Sengupta

Proceedings of the 53rd Annual Design Automation Conference, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.

[BibT_eX]

[DOI]

Mohammadmahdi R. Yousefi

Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015

Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Azadeh Davoodi

Muhammet Mustafa Ozdal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Built-In Self Optimization for Variation Resilience of Analog Filters.

[BibT_eX]

[DOI]

Jiafan Wang

Congyin Shi

Edgar Sánchez-Sinencio

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits.

[BibT_eX]

[DOI]

Jiafan Wang

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A pre-search assisted ILP approach to analog integrated circuit routing.

[BibT_eX]

[DOI]

Chia-Yu Wu

Helmut Graeb

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

GPU acceleration for PCA-based statistical static timing analysis.

[BibT_eX]

[DOI]

Yiren Shen

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Timing verification for adaptive integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Joint precision optimization and high level synthesis for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Algorithms for power-efficient QoS in application specific NoCs.

[BibT_eX]

[DOI]

Gongming Yang

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Boostable Repeater Design for Variation Resilience in VLSI Interconnects.

[BibT_eX]

[DOI]

Kyu-Nam Shim

IEEE Trans. Very Large Scale Integr. Syst., 2013

Guest editorial: Special section on cross-domain physical optimization.

[BibT_eX]

[DOI]

Cheng-Kok Koh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Resource allocation algorithms for guaranteed service in application-specific NoCs.

[BibT_eX]

[DOI]

Gongming Yang

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Power gating with block migration in chip-multiprocessor last-level caches.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Dynamic voltage and frequency scaling for shared resources in multicore processor designs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.

[BibT_eX]

[DOI]

Muhammet Mustafa Ozdal

Steven M. Burns

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Guest Editorial Special Section on the 2011 International Symposium on Physical Design.

[BibT_eX]

[DOI]

Cheng-Kok Koh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Track assignment considering crosstalk-induced performance degradation.

[BibT_eX]

[DOI]

Qiong Zhao

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience.

[BibT_eX]

[DOI]

Kyu-Nam Shim

Mohammad Asad R. Chaudhry

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies.

[BibT_eX]

[DOI]

Zakia Asad

Alexander Sprintson

VLSI Design, 2011

Simultaneous Technology Mapping and Placement for Delay Minimization.

[BibT_eX]

[DOI]

Rupesh S. Shelar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Lagrangian relaxation for gate implementation selection.

[BibT_eX]

[DOI]

Yi-Le Huang

Proceedings of the 2011 International Symposium on Physical Design, 2011

Regularity-constrained floorplanning for multi-core processors.

[BibT_eX]

[DOI]

Xi Chen

Ning Xu

Proceedings of the 2011 International Symposium on Physical Design, 2011

Gate sizing and device technology selection algorithms for high-performance industrial designs.

[BibT_eX]

[DOI]

Muhammet Mustafa Ozdal

Steven M. Burns

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Pattern Sensitive Placement Perturbation for Manufacturability.

[BibT_eX]

[DOI]

Patrik Shah

IEEE Trans. Very Large Scale Integr. Syst., 2010

Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A dual-level adaptive supply voltage system for variation resilience.

[BibT_eX]

[DOI]

Kyu-Nam Shim

José Silva-Martínez

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Accurate clock mesh sizing via sequential quadraticprogramming.

[BibT_eX]

[DOI]

Venkata Rajesh Mekala

Proceedings of the 2010 International Symposium on Physical Design, 2010

Clustering-based simultaneous task and voltage scheduling for NoC systems.

[BibT_eX]

[DOI]

Yu Yang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Detecting tangled logic structures in VLSI netlists.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Physical design techniques for optimizing RTA-induced variations.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.

[BibT_eX]

[DOI]

Yang Liu

Tong Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2009

A fast general slew constrained minimum cost buffering algorithm.

[BibT_eX]

[DOI]

Microelectron. J., 2009

A single layer zero skew clock routing in X architecture.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2009

A new algorithm for simultaneous gate sizing and threshold voltage assignment.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Impact of lithography-friendly circuit layout.

[BibT_eX]

[DOI]

Pratik J. Shah

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

GPU-based parallelization for fast circuit optimization.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Buffering in the Layout Environment.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Timing-Driven Interconnect Synthesis.

[BibT_eX]

[DOI]

Gabriel Robins

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Buffer Insertion Basics.

[BibT_eX]

[DOI]

Zhuo Li

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Power Grid Analysis and Optimization Using Algebraic Multigrid.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Robust Clock Tree Routing in the Presence of Process Variations.

[BibT_eX]

[DOI]

Uday Padmanabhan

Janet Meiling Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Buffering Interconnect for Multicore Processor Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.

[BibT_eX]

[DOI]

Integr., 2008

ASIC design flow considering lithography-induced effects.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

Low Power Gated Clock Tree Driven Placement.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Elastic Timing Scheme for Energy-Efficient and Robust Performance.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

Discrete buffer and wire sizing for link-based non-tree clock networks.

[BibT_eX]

[DOI]

Rupak Samanta

Peng Li

Proceedings of the 2008 International Symposium on Physical Design, 2008

Multi-scenario buffer insertion in multi-core processor designs.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

Gate planning during placement for gated clock network.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Built-In Proactive Tuning System for Circuit Aging Resilience.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Handling partial correlations in yield prediction.

[BibT_eX]

[DOI]

Sridhar Varadan

Janet Meiling Wang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Integrated Placement and Skew Optimization for Rotary Clocking.

[BibT_eX]

[DOI]

Frank Liu

IEEE Trans. Very Large Scale Integr. Syst., 2007

Utilizing Redundancy for Timing Critical Interconnect.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.

[BibT_eX]

[DOI]

Mosong Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2007

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.

[BibT_eX]

[DOI]

Bor-Yiing Su

Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Placement Methodology for Robust Clocking.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.

[BibT_eX]

[DOI]

Yang Liu

Tong Zhang

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An Efficient Algorithm for RLC Buffer Insertion.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Pattern sensitive placement for manufacturability.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Modeling, optimization and control of rotary traveling-wave oscillator.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Unified adaptivity optimization of clock and logic signals.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Gate Sizing For Cell Library-Based Designs.

[BibT_eX]

[DOI]

Mahesh Ketkar

Proceedings of the 44th Design Automation Conference, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Antenna Avoidance in Layer Assignment.

[BibT_eX]

[DOI]

Di Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing clock skew variability via crosslinks.

[BibT_eX]

[DOI]

Anand Rajaram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low Power Trellis Decoder with Overscaled Supply Voltage.

[BibT_eX]

[DOI]

Yang Liu

Tong Zhang

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

An Improved AMG-based Method for Fast Power Grid Analysis.

[BibT_eX]

[DOI]

Cheng Zhuo

Kangsheng Chen

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient Model Update for General Link-Insertion Networks.

[BibT_eX]

[DOI]

Zhuo Feng

Peng Li

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.

[BibT_eX]

[DOI]

Bor-Yiing Su

Yao-Wen Chang

Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical clock tree routing for robustness to process variations.

[BibT_eX]

[DOI]

Uday Padmanabhan

Janet Meiling Wang

Proceedings of the 2006 International Symposium on Physical Design, 2006

High performance clock routing in X-architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fast decap allocation based on algebraic multigrid.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Combinatorial algorithms for fast clock mesh optimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Clock buffer polarity assignment for power noise reduction.

[BibT_eX]

[DOI]

Rupak Samanta

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new RLC buffer insertion algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Integrated placement and skew optimization for rotary clocking.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Associative skew clock routing for difficult instances.

[BibT_eX]

[DOI]

Min-Seok Kim

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Steiner network construction for timing critical nets.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Fast algorithms for slew constrained minimum cost buffering.

[BibT_eX]

[DOI]

Charles J. Alpert

Shrirang K. Karandikar

Zhuo Li

Proceedings of the 43rd Design Automation Conference, 2006

Standard cell characterization considering lithography induced variations.

[BibT_eX]

[DOI]

Sorin Dobre

Proceedings of the 43rd Design Automation Conference, 2006

2005

An efficient merging scheme for prescribed skew clock routing.

[BibT_eX]

[DOI]

Rishi Chaturvedi

IEEE Trans. Very Large Scale Integr. Syst., 2005

Navigating Register Placement for Low Power Clock Network Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Coupling aware timing optimization and antenna avoidance in layer assignment.

[BibT_eX]

[DOI]

Di Wu

Proceedings of the 2005 International Symposium on Physical Design, 2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.

[BibT_eX]

[DOI]

Anand Rajaram

David Z. Pan

Proceedings of the 2005 International Symposium on Physical Design, 2005

DiCER: distributed and cost-effective redundancy for variation tolerance.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Practical techniques to reduce skew and its variations in buffered clock networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Path based buffer insertion.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Navigating registers in placement for clock network minimization.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Timing driven track routing considering coupling capacitance.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Skew scheduling and clock routing for improved tolerance to process variations.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Making fast buffer insertion even faster via approximation techniques.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Library cell layout with Alt-PSM compliance and composability.

[BibT_eX]

[DOI]

Puneet Dhawan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A methodology for the simultaneous design of supply and signal networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Porosity-aware buffered Steiner tree construction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Exploiting level sensitive latches in wire pipelining.

[BibT_eX]

[DOI]

V. Seth

Min Zhao

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Accurate estimation of global buffer delay within a floorplan.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Reducing clock skew variability via cross links.

[BibT_eX]

[DOI]

Anand Rajaram

Proceedings of the 41th Design Automation Conference, 2004

Fast and flexible buffer trees that navigate the physical layout environment.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Layer assignment for crosstalk risk minimization.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A place and route aware buffered Steiner tree construction.

[BibT_eX]

[DOI]

Charles J. Alpert

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Process variation aware clock tree routing.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Porosity aware buffered steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.

[BibT_eX]

[DOI]

Rishi Chaturvedi

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

A timing-constrained simultaneous global routing algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Buffer insertion with adaptive blockage avoidance.

[BibT_eX]

[DOI]

Proceedings of 2002 International Symposium on Physical Design, 2002

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.

[BibT_eX]

[DOI]

Chandramouli V. Kashyap

Stephen T. Quay

Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion-driven codesign of power and signal networks.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

A survey on multi-net global routing for integrated circuits.

[BibT_eX]

[DOI]

Integr., 2001

Buffered Steiner trees for difficult instances.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Steiner tree optimization for buffers. Blockages and bays.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Performance Driven Global Routing Through Gradual Refinement.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Practical Methodology for Early Buffer and Wire Resource Allocation.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Non-Hanan routing.

[BibT_eX]

[DOI]

Huibo Hou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

FAR-DS: Full-Plane AWE Routing with Driver Sizing.

[BibT_eX]

[DOI]