Changhyun Kim

According to our database1, Changhyun Kim authored at least 30 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to low voltage, high performance, high density memory design".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020

x64Unpack: Hybrid Emulation Unpacker for 64-bit Windows Environments and Detailed Analysis Results on VMProtect 3.4.
IEEE Access, 2020

2019

DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture.
Proceedings of the ACM International Conference on Supercomputing, 2019

2017
Time-delay control based on a nonlinear vehicle lateral dynamics.
Proceedings of the 11th Asian Control Conference, 2017

2016
Contention-based congestion management in large-scale networks.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
16.6 Double-side CMOS-CNT biosensor array with padless structure for simple bare-die measurements in a medical environment.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Extending bufferless on-chip networks to high-throughput workloads.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
Example-Based Super-Resolution via Structure Analysis of Patches.
IEEE Signal Process. Lett., 2013

2011
Resolution Improvement of Infrared Images Using Visible Image Information.
IEEE Signal Process. Lett., 2011

2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.
IEEE J. Solid State Circuits, 2010

Robust learning-based super-resolution.
Proceedings of the International Conference on Image Processing, 2010

Infrared image enhancement based on an aligned high resolution visible image.
Proceedings of the International Conference on Image Processing, 2010

2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009


Improvement on learning-based super-resolution by adopting residual information and patch reliability.
Proceedings of the International Conference on Image Processing, 2009

2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008

What is Needed the Most in MT-Supported Paper Writing.
Proceedings of the 22nd Pacific Asia Conference on Language, Information and Computation, 2008

A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007

2006
Advances in Memory Technology.
Proceedings of the 32nd International Conference on Very Large Data Bases, 2006

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Future Memory Technology Trends and Challenges.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications.
IEICE Trans. Electron., 2005

2004
A low power capacitive coupled bus interface based on pulsed signaling.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
Verb Pattern Based Korean-Chinese Machine Translation System.
Proceedings of the 16th Pacific Asia Conference on Language, Information and Computation, 2002

Korean-Chinese Machine Translation Based on Verb Patterns.
Proceedings of the Machine Translation: From Research to Real Users, 2002


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