Shekhar Y. Borkar

According to our database1, Shekhar Y. Borkar authored at least 85 papers between 1988 and 2017.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to low power digital circuits in deep submicron technology".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2017
Traleika Glacier: A hardware-software co-designed approach to exascale computing.
Parallel Computing, 2017

2016
Extreme Energy Efficiency by Near Threshold Voltage Operation.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
J. Solid-State Circuits, 2015

2014
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Resiliency for many-core system on a chip.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.
J. Solid-State Circuits, 2013

Centip3De demonstrates more than Moore...: technical perspective.
Commun. ACM, 2013

EP3: Empowering the killer SoC applications of 2020.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Exascale Computing - A Fact or a Fiction?
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Runnemede: An architecture for Ubiquitous High-Performance Computing.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Power management and delivery for high-performance microprocessors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


On the Role of Co-design in High Performance Computing.
Proceedings of the Transition of HPC Towards Exascale Computing, 2012

Near-threshold voltage (NTV) design: opportunities and challenges.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
J. Solid-State Circuits, 2011

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
J. Solid-State Circuits, 2011

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.
IET Computers & Digital Techniques, 2011

The future of microprocessors.
Commun. ACM, 2011

3DICs for tera-scale computing: a case study.
Proceedings of the 2011 International Symposium on Physical Design, 2011

3D integration for energy efficient system design.
Proceedings of the 48th Design Automation Conference, 2011

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.
J. Solid-State Circuits, 2010

Want to be a bug buster?
Commun. ACM, 2010

Future of interconnect fabric: a contrarian view.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010


Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

The semiconductor industry in 2025.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
J. Solid-State Circuits, 2009

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS.
J. Solid-State Circuits, 2009

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Circuit techniques for dynamic variation tolerance.
Proceedings of the 46th Design Automation Conference, 2009

Design perspectives on 22nm CMOS and beyond.
Proceedings of the 46th Design Automation Conference, 2009

2008
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
J. Solid-State Circuits, 2008

A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS.
J. Solid-State Circuits, 2008

Thousand-Core Chips [Roundtable].
IEEE Design & Test of Computers, 2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Custom is from Venus and synthesis from Mars.
Proceedings of the 45th Design Automation Conference, 2008

2007
A 5-GHz Mesh Interconnect for a Teraflops Processor.
IEEE Micro, 2007

A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Future of on-chip interconnection architectures.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Microprocessors in the era of terascale integration.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Thousand Core ChipsA Technology Perspective.
Proceedings of the 44th Design Automation Conference, 2007

2006
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. VLSI Syst., 2006

Tackling variability and reliability challenges.
IEEE Design & Test of Computers, 2006

Probabilistic amp; Statistical Design - the Wave of the Future.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Introduction to panel discussion Probabilistic & statistical design - the wave of the future.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Tomorrow's analog: just dead or just different?
Proceedings of the 43rd Design Automation Conference, 2006

Electronics beyond nano-scale CMOS.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation.
IEEE Micro, 2005

VLSI Design Challenges for Gigascale Integration.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004
Microarchitecture and Design Challenges for Gigascale Integration.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Is statistical timing statistically significant?
Proceedings of the 41th Design Automation Conference, 2004

Design and reliability challenges in nanometer technologies.
Proceedings of the 41th Design Automation Conference, 2004

2003
Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law.
ACM Queue, 2003

Exponential Challenges, Exponential Rewards - The future of Moore's Law.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Nanometer design: place your bets.
Proceedings of the 40th Design Automation Conference, 2003

Parameter variations and impact on circuits and microarchitecture.
Proceedings of the 40th Design Automation Conference, 2003

2002
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. VLSI Syst., 2002

Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Sub-90nm technologies: challenges and opportunities for CAD.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Life is CMOS: why chase the life after?
Proceedings of the 39th Design Automation Conference, 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002

2001
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Scaling of stack effect and its application for leakage reduction.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A low-leakage dynamic multi-ported register file in 0.13mm CMOS.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Panel: Is Nanometer Design Under Control?
Proceedings of the 38th Design Automation Conference, 2001

Low power design challenges for the decade (invited talk).
Proceedings of ASP-DAC 2001, 2001

2000
Low power and high performance design challenges in future technologies.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Design challenges of technology scaling.
IEEE Micro, 1999

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Technology and design challenges for low power and high performance.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1990
Supporting Systolic and Memory Communciation in iWarp.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1988
Warp: an integrated solution of high-speed parallel computing.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988


  Loading...