Francesco Regazzoni

According to our database1, Francesco Regazzoni authored at least 116 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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PhD thesis 
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Bibliography

2020
Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography.
ACM Trans. Embedded Comput. Syst., 2020

Friet: An Authenticated Encryption Scheme with Built-in Fault Detection.
IACR Cryptol. ePrint Arch., 2020

An Instruction Set Extension to Support Software-Based Masking.
IACR Cryptol. ePrint Arch., 2020

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Black-Hat High-Level Synthesis: Myth or Reality?
IEEE Trans. Very Large Scale Integr. Syst., 2019

The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Compact circuits for combined AES encryption/decryption.
J. Cryptogr. Eng., 2019

Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers.
IACR Cryptol. ePrint Arch., 2019

Fault Attack Countermeasures for Error Samplers in Lattice-Based Cryptography.
IACR Cryptol. ePrint Arch., 2019

Swap and Rotate: Lightweight linear layers for SPN-based blockciphers.
IACR Cryptol. ePrint Arch., 2019

Guest Editors' Introduction.
Embedded Systems Letters, 2019

Secure Composition for Hardware Systems (Dagstuhl Seminar 19301).
Dagstuhl Reports, 2019

Post-Quantum Lattice-Based Cryptography Implementations: A Survey.
ACM Comput. Surv., 2019

Fault Sensitivity Analysis of Lattice-Based Post-Quantum Cryptographic Components.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Elicitation of technical requirements in large research projects: the CERBERO approach.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

PlaidML-HE: Acceleration of Deep Learning Kernels to Compute on Encrypted Data.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Security in Autonomous Systems.
Proceedings of the 24th IEEE European Test Symposium, 2019

High-Level Synthesis of Benevolent Trojans.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

2018
Towards Low Energy Stream Ciphers.
IACR Trans. Symmetric Cryptol., 2018

On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography.
IEEE Trans. Computers, 2018

Towards Lightweight Cryptographic Primitives with Built-in Fault-Detection.
IACR Cryptol. ePrint Arch., 2018

When Theory Meets Practice: A Framework for Robust Profiled Side-channel Analysis.
IACR Cryptol. ePrint Arch., 2018

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow.
IACR Cryptol. ePrint Arch., 2018

Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography.
IACR Cryptol. ePrint Arch., 2018

Lightweight Circuits with Shift and Swap.
IACR Cryptol. ePrint Arch., 2018

Customized Instructions for Protection Against Memory Integrity Attacks.
Embedded Systems Letters, 2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.
Embedded Systems Letters, 2018

Quantum era challenges for classical computers.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Session details: Security threats caused by novel technologies.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Security: the dark side of approximate computing?
Proceedings of the International Conference on Computer-Aided Design, 2018

Inverse gating for low energy encryption.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Exploring the Vulnerability of R-LWE Encryption to Fault Attacks.
Proceedings of the Fifth Workshop on Cryptography and Security in Computing Systems, 2018

Physical Protection of Lattice-Based Cryptography: Challenges and Solutions.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

TAO: techniques for algorithm-level obfuscation during high-level synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

ASHES 2018- Workshop on Attacks and Solutions in Hardware Security.
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

SCA-Resistance for AES: How Cheap Can We Go?
Proceedings of the Progress in Cryptology - AFRICACRYPT 2018, 2018

2017
An Investigation of Sources of Randomness Within Discrete Gaussian Sampling.
IACR Cryptol. ePrint Arch., 2017

Introduction to hardware-oriented security for MPSoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

The design space of the number theoretic transform: A survey.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Special session on architectures and design tools for secure embedded systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Efficient configurations for block ciphers with unified ENC/DEC paths.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Counteracting malicious faults in cryptographic circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Cross-layer design of reconfigurable cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient arithmetic for lattice-based cryptography: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Securing the hardware of cyber-physical systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Embedded systems education: job market expectations.
SIGBED Rev., 2016

Atomic-AES v 2.0.
IACR Cryptol. ePrint Arch., 2016

Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core.
IACR Cryptol. ePrint Arch., 2016

Evaluating physically unclonable functions on a large set of FPGAs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Physical Attacks and Beyond.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

Lattice-based cryptography: From reconfigurable hardware to ASIC.
Proceedings of the International Symposium on Integrated Circuits, 2016

Round gating for low energy block ciphers.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Instruction Set Extensions for secure applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Standard lattices in hardware.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Secure architectures of future emerging cryptography <i>SAFEcrypto</i>.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Adaptable AES implementation with power-gating support.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Automatic Application of Power Analysis Countermeasures.
IEEE Trans. Computers, 2015

Exploring Energy Efficiency of Lightweight Block Ciphers.
IACR Cryptol. ePrint Arch., 2015

Midori: A Block Cipher for Low Energy (Extended Version).
IACR Cryptol. ePrint Arch., 2015

Exploring the energy consumption of lightweight blockciphers in FPGA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A survey on hardware trojan detection techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Simulation and analysis of negative-bias temperature instability aging on power analysis attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

200 MS/s ADC implemented in a FPGA employing TDCs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Physical attacks, introduction and application to embedded processors.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Fault attacks, injection techniques and tools for simulation.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Design methodologies for securing cyber-physical systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Midori: A Block Cipher for Low Energy.
Proceedings of the Advances in Cryptology - ASIACRYPT 2015 - 21st International Conference on the Theory and Application of Cryptology and Information Security, Auckland, New Zealand, November 29, 2015

2014
A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.
IEEE Trans. Emerg. Top. Comput., 2014

Stealthy dopant-level hardware Trojans: extended version.
J. Cryptogr. Eng., 2014

Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks.
IACR Cryptol. ePrint Arch., 2014

Lightweight cryptography for constrained devices.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

THOR - The hardware onion router.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Accelerating differential power analysis on heterogeneous systems.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

SPADs for quantum random number generators and beyond.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

A Survey of Recent Results in FPGA Security and Intellectual Property Protection.
Proceedings of the Secure Smart Embedded Devices, Platforms and Applications, 2014

2013
ALE: AES-Based Lightweight Authenticated Encryption.
Proceedings of the Fast Software Encryption - 20th International Workshop, 2013

An EDA-friendly protection scheme against side-channel attacks.
Proceedings of the Design, Automation and Test in Europe, 2013

Single-photon image sensors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Stealthy Dopant-Level Hardware Trojans.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

Sleuth: Automated Verification of Software Power Analysis Countermeasures.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

2012
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks.
Proceedings of the Fault Analysis in Cryptography, 2012

A Fast ULV Logic Synthesis Flow in Many-V<sub>t</sub> CMOS Processes for Minimum Energy Under Timing Constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices.
IACR Cryptol. ePrint Arch., 2012

LEXCOMM: A low energy, secure and flexible communication protocol for a heterogenous body sensor network.
Proceedings of 2012 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2012

Security Enhanced Linux on embedded systems: A hardware-accelerated implementation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2012, 2012

2011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptogr. Eng., 2011

Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.
Proceedings of the 48th Design Automation Conference, 2011

A first step towards automatic application of power analysis countermeasures.
Proceedings of the 48th Design Automation Conference, 2011

Fresh Re-keying II: Securing Multiple Parties against Side-Channel and Fault Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2011

Compact FPGA Implementations of the Five SHA-3 Finalists.
Proceedings of the Smart Card Research and Advanced Applications, 2011

2010
Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software.
Proceedings of the Trusted Systems - Second International Conference, 2010

A reconfigurable multiprocessor architecture for a reliable face recognition implementation.
Proceedings of the Design, Automation and Test in Europe, 2010

Countermeasures against fault attacks on software implemented AES: effectiveness and cost.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices.
Proceedings of the Progress in Cryptology, 2010

2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009

Breaking ECC2K-130.
IACR Cryptol. ePrint Arch., 2009

The Certicom Challenges ECC2-X.
IACR Cryptol. ePrint Arch., 2009

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm.
Proceedings of the SECRYPT 2008, 2008

Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Hardware scheduling support in SMP architectures.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Hardware/software partitioning of operating systems: a behavioral synthesis approach.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Speeding Up AES By Extending a 32 bit Processor Instruction Set.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Automatic synthesis of the Hardware/Software Interface.
Proceedings of the Forum on specification and Design Languages, 2005


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