Wei Zhang

According to our database1, Wei Zhang authored at least 118 papers between 2005 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Accelerate pattern recognition for cyber security analysis.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
IEEE Trans. Multi-Scale Computing Systems, 2018

Analyzing Data Cache Related Preemption Delay With Multiple Preemptions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018

FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs.
IEEE Trans. Computers, 2018

SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs.
IEEE Trans. VLSI Syst., 2017

A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency.
IEEE Trans. on Circuits and Systems, 2017

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures.
CSSP, 2017

Fracturable DSP Block for Multi-context Reconfigurable Architectures.
CSSP, 2017

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A hybrid approach to cache management in heterogeneous CPU-FPGA platforms.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Decision tree based hardware power monitoring for run time dynamic power management in FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

PAAS: A system level simulator for heterogeneous computing architectures.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Low-Power FPGA Design Using Memoization-Based Approximate Computing.
IEEE Trans. VLSI Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
IEEE Trans. VLSI Syst., 2016

A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems.
IEEE Trans. VLSI Syst., 2016

Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems.
IEEE Trans. VLSI Syst., 2016

Melia: A MapReduce Framework on OpenCL-Based FPGAs.
IEEE Trans. Parallel Distrib. Syst., 2016

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.
ACM Trans. Design Autom. Electr. Syst., 2016

Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware.
IEEE Trans. Information Forensics and Security, 2016

Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Online malware defense using attack behavior model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A performance analysis framework for optimizing OpenCL applications on FPGAs.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Modular Placement for Interposer based Multi-FPGA Systems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Relational query processing on OpenCL-based FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

HeteroSim: A heterogeneous CPU-FPGA simulator.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

A discrete thermal controller for chip-multiprocessors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A racetrack memory based in-memory booth multiplier for cryptography application.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. VLSI Syst., 2015

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
IEEE Trans. VLSI Syst., 2015

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. VLSI Syst., 2015

Hierarchical Library Based Power Estimator for Versatile FPGAs.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

A study of data partitioning on OpenCL-based FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Hierarchical library based power estimator for versatile FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Improving Data Partitioning Performance on OpenCL-Based FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2014

Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention.
IEEE Trans. VLSI Syst., 2014

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
IEEE Trans. VLSI Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
JETC, 2014

Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Sum of products: Computation using modular thermometer codes.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014

Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Reconfigurable DSP block design for dynamically reconfigurable architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-power pipelined MAC architecture using Baugh-Wooley based multiplier.
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Towards automatic partial reconfiguration in FPGAs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

BMP: a fast B*-tree based modular placer for FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Hierarchical library-based power estimator for versatile FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A low cost acceleration method for hardware trojan detection based on fan-out cone analysis.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

An extended framework for worst-case throughput analysis with router constraint.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Soft error mitigation through selection of noninvert implication paths.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

A New RNS based DA Approach for Inner Product Computation.
IEEE Trans. on Circuits and Systems, 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

NBTI-aware circuit node criticality computation.
JETC, 2013

A hardware security scheme for RRAM-based FPGA.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs.
IEEE Trans. VLSI Syst., 2012

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.
IEEE Trans. VLSI Syst., 2012

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
JETC, 2012

A physical design tool for carbon nanotube field-effect transistor circuits.
JETC, 2012

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel peripheral circuit for RRAM-based LUT.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Distributed thermal-aware task scheduling for 3D Network-on-Chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Non-volatile 3D stacking RRAM-based FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A Look Up Table design with 3D bipolar RRAMs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Fine-grained dynamic voltage scaling on OLED display.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
Embedded Systems Letters, 2011

NEMS based thermal management for 3D many-core system.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.
Proceedings of the Design, Automation and Test in Europe, 2011

Power Dissipation.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture.
JETC, 2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

2009
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs.
IEEE Micro, 2009

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.
JETC, 2009

A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture.
JETC, 2009

A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.
JETC, 2009

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
Proceedings of the 44th Design Automation Conference, 2007

2006
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
Proceedings of the 43rd Design Automation Conference, 2006

2005
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005


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