Yu Cao

According to our database1, Yu Cao authored at least 100 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
J. Solid-State Circuits, 2019

Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning.
JETC, 2019

Efficient Network Construction Through Structural Plasticity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.
CoRR, 2019

Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches.
CoRR, 2019

Single-Net Continual Learning with Progressive Segmented Training (PST).
CoRR, 2019

CGaP: Continuous Growth and Pruning for Efficient Deep Learning.
CoRR, 2019

Efficient Network Construction through Structural Plasticity.
CoRR, 2019

2018
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA.
IEEE Trans. VLSI Syst., 2018

Process Scalability of Pulse-Based Circuits for Analog Image Convolution.
IEEE Trans. on Circuits and Systems, 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
JETC, 2018

Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning.
JETC, 2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integration, 2018

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain.
CoRR, 2018

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Towards a Wearable Cough Detector Based on Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
RTN in Scaled Transistors for On-Chip Random Seed Generation.
IEEE Trans. VLSI Syst., 2017

Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance.
IEEE Trans. Multi-Scale Computing Systems, 2017

Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning.
JETC, 2017

Improving efficiency in sparse learning with the feedforward inhibitory motif.
Neurocomputing, 2017

Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations.
CoRR, 2017

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

End-to-end scalable FPGA accelerator for deep residual networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation.
IEEE Trans. on Circuits and Systems, 2016

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol., 2016

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Reducing the Model Order of Deep Neural Networks Using Information Theory.
CoRR, 2016

Reducing the Model Order of Deep Neural Networks Using Information Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design of a reliable RRAM-based PUF for compact hardware security primitives.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

High-performance face detection with CPU-FPGA acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Bi-Level Rare Temporal Pattern Detection.
Proceedings of the IEEE 16th International Conference on Data Mining, 2016

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Ranking the parameters of deep neural networks using the fisher information.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On-chip Sparse Learning with Resistive Cross-point Array Architecture.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram.
Signal Processing Systems, 2014

The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits.
Fundam. Inform., 2014

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

2013
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation.
IEEE Trans. on Circuits and Systems, 2013

NBTI-aware circuit node criticality computation.
JETC, 2013

Compact modeling of STT-MTJ for SPICE simulation.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding.
EURASIP J. Adv. Sig. Proc., 2012

Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

An analytical approach to efficient circuit variability analysis in scaled CMOS design.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Design benchmarking to 7nm with FinFET predictive technology models.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Hierarchical modeling of Phase Change memory for reliable design.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Exploring sub-20nm FinFET design with predictive technology models.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Predictive Technology Model for Robust Nanoelectronic Design
Integrated Circuits and Systems, Springer, ISBN: 978-1-4614-0445-3, 2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.
IEEE Trans. VLSI Syst., 2011

Circuit-level delay modeling considering both TDDB and NBTI.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.
IEEE Trans. VLSI Syst., 2010

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.
IEEE Trans. VLSI Syst., 2010

Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design.
IEEE Design & Test of Computers, 2010

2009
Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation.
IEEE Trans. VLSI Syst., 2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
International Journal of Parallel Programming, 2009

The Predictive Technology Model in the Late Silicon Era and Beyond.
Foundations and Trends in Electronic Design Automation, 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Modeling of layout-dependent stress effect in CMOS design.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Gate replacement techniques for simultaneous leakage and aging optimization.
Proceedings of the Design, Automation and Test in Europe, 2009

Variability analysis under layout pattern-dependent rapid-thermal annealing process.
Proceedings of the 46th Design Automation Conference, 2009

A framework for estimating NBTI degradation of microarchitectural components.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proceedings of the IEEE, 2008

Scalable model for predicting the effect of negative bias temperature instability for reliable design.
IET Circuits, Devices & Systems, 2008

Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
Proceedings of the 2008 IEEE International Test Conference, 2008

Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.
Proceedings of the 45th Design Automation Conference, 2008

Statistical prediction of circuit aging under process variations.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A New Simulation Method for NBTI Analysis in SPICE Environment.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An efficient method to identify critical gates under circuit aging.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Fast statistical circuit analysis with finite-point based transistor model.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

The Impact of NBTI on the Performance of Combinational and Sequential Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
Proceedings of the 44th Design Automation Conference, 2007

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
SRAM Cell Optimization for Ultra-Low Power Standby.
J. Low Power Electronics, 2006

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.
J. Low Power Electronics, 2006

LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Modeling and minimization of PMOS NBTI effect for robust nanometer design.
Proceedings of the 43rd Design Automation Conference, 2006

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
Proceedings of the 43rd Design Automation Conference, 2006

Predictive Modeling of the NBTI Effect for Reliable Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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