Huazhong Yang
Orcid: 0000-0003-2421-353X
According to our database1,
Huazhong Yang
authored at least 635 papers
between 1999 and 2025.
Collaborative distances:
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Bibliography
2025
Online Planning for Multi-UAV Pursuit-Evasion in Unknown Environments Using Deep Reinforcement Learning.
IEEE Robotics Autom. Lett., August, 2025
What Matters in Learning a Zero-Shot Sim-to-Real RL Policy for Quadrotor Control? A Comprehensive Study.
IEEE Robotics Autom. Lett., July, 2025
Enabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor.
IEEE J. Solid State Circuits, July, 2025
R2R: Efficiently Navigating Divergent Reasoning Paths with Small-Large Model Token Routing.
CoRR, May, 2025
CoRR, May, 2025
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit.
IEEE J. Solid State Circuits, March, 2025
Enhancing Memory Efficiency in Large Language Model Training Through Chronos-aware Pipeline Parallelism.
CoRR, March, 2025
A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2025
IEEE Robotics Autom. Lett., February, 2025
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference.
IEEE J. Solid State Circuits, February, 2025
Policy-to-Language: Train LLMs to Explain Decisions with Flow-Matching Generated Rewards.
CoRR, February, 2025
FrameFusion: Combining Similarity and Importance for Video Token Reduction on Large Visual Language Models.
CoRR, January, 2025
1.78mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian Cache Scheduler.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
3D-Domino: Ultra-Dense High-Accuracy 3D eDRAM-ROM Compute-In-Memory Based on CAA-IGZO TFT for Edge Large-Scale Model Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A Threshold-Voltage Compensation Circuit for Organic Thin-Film Transistor Active-Matrix Neurostimulation System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Kung-Fu: An Energy-Efficient Compute-In-Memory Approach for Neural Network Inference Using Multi-Level Binary Computing Fusion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
ViDiT-Q: Efficient and Accurate Quantization of Diffusion Transformers for Image and Video Generation.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
Linear Combination of Saved Checkpoints Makes Consistency and Diffusion Models Better.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
Presto: A Unified RISC-V-Compatible SoC for Multi-Scheme FHE Acceleration over Module Lattice.
Proceedings of the IEEE Hot Chips 37 Symposium, 2025
ADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNs.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
PARO: Hardware-Software Co-design with Pattern-aware Reorder-based Attention Quantization in Video Generation Models.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
PUFiM: A Robust and Efficient FeFET-Based Security Solution Merging Physical Unclonable Function with Compute-in-Memory for Edge AI.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2025
A 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
A Fully Quantized Training Accelerator for Diffusion Network With Tensor Type & Noise Strength Aware Precision Scheduling.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2024
A Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Trans. Circuits Syst. Video Technol., September, 2024
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis.
IEEE J. Solid State Circuits, September, 2024
A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching.
IEEE J. Solid State Circuits, September, 2024
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.
IEEE J. Solid State Circuits, August, 2024
IEEE Trans. Circuits Syst. Video Technol., June, 2024
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm<sup>2</sup> Density in 65-nm CMOS.
IEEE J. Solid State Circuits, June, 2024
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.
IEEE J. Solid State Circuits, May, 2024
ACM Trans. Design Autom. Electr. Syst., March, 2024
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories.
ACM Trans. Design Autom. Electr. Syst., January, 2024
IEEE Robotics Autom. Lett., January, 2024
IEEE Trans. Ind. Electron., 2024
A Highly Scalable Integrated Voltage Equalizer Based on Parallel-Transformers for High-Voltage Energy Storage Systems.
IEEE Trans. Ind. Electron., 2024
GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.
IEEE Trans. Emerg. Top. Comput., 2024
Multi-UAV Pursuit-Evasion with Online Planning in Unknown Environments by Deep Reinforcement Learning.
CoRR, 2024
Efficient Expert Pruning for Sparse Mixture-of-Experts Language Models: Enhancing Performance and Reducing Inference Costs.
CoRR, 2024
CoRR, 2024
ViDiT-Q: Efficient and Accurate Quantization of Diffusion Transformers for Image and Video Generation.
CoRR, 2024
CityLight: A Universal Model Towards Real-world City-scale Traffic Signal Control Coordination.
CoRR, 2024
Linear Combination of Saved Checkpoints Makes Consistency and Diffusion Models Better.
CoRR, 2024
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024
34.7 A 28nm 2.4Mb/mm<sup>2</sup> 6.9 - 16.3TOPS/mm<sup>2</sup> eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Proceedings of the Twelfth International Conference on Learning Representations, 2024
Proceedings of the Twelfth International Conference on Learning Representations, 2024
NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Towards Floating Point-Based Attention-Free LLM: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack Through Frequency-Triggered Key Generation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
FlashEval: Towards Fast and Accurate Evaluation of Text-to-Image Diffusion Generative Models.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024
A 28nm 8928Kb/mm<sup>2</sup>-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
Multi-Agent Vulnerability Discovery for Autonomous Driving Policy by Finding AV-Responsible Scenarios.
Proceedings of the 20th IEEE International Conference on Automation Science and Engineering, 2024
A Unified Microrobotic Visual-Perception Processor with 62.2-FPS/mm<sup>2</sup> and 103-uJ/frame Navigation in 28nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
A 28nm 166.9 TOPS/W x Mb/mm<sup>2</sup> DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Accelerate Multi-Agent Reinforcement Learning in Zero-Sum Games with Subgame Curriculum Learning.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
CoGNN: An Algorithm-Hardware Co-Design Approach to Accelerate GNN Inference With Minibatch Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Gibbon: An Efficient Co-Exploration Framework of NN Model and Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles.
IEEE Trans. Ind. Electron., July, 2023
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
A Generic Graph-Based Neural Architecture Encoding Scheme With Multifaceted Information.
IEEE Trans. Pattern Anal. Mach. Intell., July, 2023
A Single-Magnetic Bidirectional Integrated Equalizer Using Multi-Winding Transformer and Voltage Multiplier for Hybrid Energy Storage System.
IEEE Trans. Veh. Technol., June, 2023
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective.
IEEE Trans. Computers, May, 2023
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
CoRR, 2023
Predicting Coronary Heart Disease Using an Improved LightGBM Model: Performance Analysis and Comparison.
IEEE Access, 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the International Conference on Machine Learning, 2023
Ada3D : Exploiting the Spatial Redundancy with Adaptive Inference for Efficient 3D Object Detection.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
TSTC: Two-Level Sparsity Tensor Core Enabling both Algorithm Flexibility and Hardware Efficiency.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Minimizing Communication Conflicts in Network-On-Chip Based Processing-In-Memory Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Processing-In-Hierarchical-Memory Architecture for Billion-Scale Approximate Nearest Neighbor Search.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Memory-Efficient and Real-Time SPAD-based dToF Depth Sensor with Spatial and Statistical Correlation.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A 28nm 1.07TFLOPS/mm<sup>2</sup> Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Asynchronous Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-Robot Cooperative Exploration.
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
Ensemble-in-One: Ensemble Learning within Random Gated Networks for Enhanced Adversarial Robustness.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud.
ACM Trans. Reconfigurable Technol. Syst., 2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Senputing: An Ultra-Low-Power Always-On Vision Perception Chip Featuring the Deep Fusion of Sensing and Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A community effort to assess and improve computerized interpretation of 12-lead resting electrocardiogram.
Medical Biol. Eng. Comput., 2022
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
IEEE J. Solid State Circuits, 2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.
IEEE J. Solid State Circuits, 2022
CoRR, 2022
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.
CoRR, 2022
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph.
CoRR, 2022
ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key.
CoRR, 2022
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.
CoRR, 2022
Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2022
A Mobile Robot Experiment System with Lightweight Simulator Generator for Deep Reinforcement Learning Algorithm.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2022
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the 23rd IEEE International Conference on Mobile Data Management, 2022
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Explore-Bench: Data Sets, Metrics and Evaluations for Frontier-based and Deep-reinforcement-learning-based Autonomous Exploration.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the Computer Vision - ECCV 2022, 2022
Proceedings of the Computer Vision - ECCV 2022, 2022
Exploiting Parallelism with Vertex-Clustering in Processing-In-Memory-based GCN Accelerators.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst., 2021
ACM Trans. Design Autom. Electr. Syst., 2021
ACM Trans. Design Autom. Electr. Syst., 2021
Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
MACSen: A Processing-In-Sensor Architecture Integrating MAC Operations Into Image Sensor for Ultra-Low-Power BNN-Based Intelligent Visual Perception.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
NS-FDN: Near-Sensor Processing Architecture of Feature-Configurable Distributed Network for Beyond-Real-Time Always-on Keyword Spotting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Signal Process. Lett., 2021
IEEE Signal Process. Lett., 2021
CLECG: A Novel Contrastive Learning Framework for Electrocardiogram Arrhythmia Classification.
IEEE Signal Process. Lett., 2021
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.
IEEE J. Solid State Circuits, 2021
Inter-patient ECG arrhythmia heartbeat classification based on unsupervised domain adaptation.
Neurocomputing, 2021
Multi-Agent Vulnerability Discovery for Autonomous Driving with Hazard Arbitration Reward.
CoRR, 2021
Ensemble-in-One: Learning Ensemble within Random Gated Networks for Enhanced Adversarial Robustness.
CoRR, 2021
Low-Cost Multi-Agent Navigation via Reinforcement Learning With Multi-Fidelity Simulator.
IEEE Access, 2021
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Variational Automatic Curriculum Learning for Sparse-Reward Cooperative Multi-Agent Problems.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Reducing Signal Swing Overheads to Only 8% in Background 3<sup>rd</sup>-Order Inter-Stage Gain Error Calibration for Pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Exploiting Online Locality and Reduction Parallelism for Sampled Dense Matrix Multiplication on GPUs.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-FPGA AI Systems in the Cloud.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching.
Proceedings of the 47th ESSCIRC 2021, 2021
Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function.
Proceedings of the 47th ESSCIRC 2021, 2021
Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR application.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst., 2020
NS-CIM: A Current-Mode Computation-in-Memory Architecture Enabling Near-Sensor Processing for Intelligent IoT Vision Nodes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
IEEE Trans. Computers, 2020
The Role and Challenges of Body Channel Communication in Wearable Flexible Electronics.
IEEE Trans. Biomed. Circuits Syst., 2020
Sensors, 2020
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
Multi-shot NAS for Discovering Adversarially Robust Convolutional Neural Architectures at Targeted Capacities.
CoRR, 2020
BARS: Joint Search of Cell Topology and Layout for Accurate and Efficient Binary ARchitectures.
CoRR, 2020
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020
CoRR, 2020
MSP-MFCC: Energy-Efficient MFCC Feature Extraction Method With Mixed-Signal Processing Architecture for Wearable Speech Recognition Applications.
IEEE Access, 2020
GE-SpMM: general-purpose sparse matrix-matrix multiplication on GPUs for graph neural networks.
Proceedings of the International Conference for High Performance Computing, 2020
Optimization and Evaluation of Energy-Efficient Mixed-Signal MFCC Feature Extraction Architecture.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
RARA: Dataflow Based Error Compensation Methods with Runtime Accuracy-Reconfigurable Adder.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
NS-KWS: joint optimization of near-sensor processing architecture and low-precision GRU for always-on keyword spotting.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
High-Quality Single-Model Deep Video Compression with Frame-Conv3D and Multi-frame Differential Modulation.
Proceedings of the Computer Vision - ECCV 2020, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing Efficiency.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Attentional Separation-and-Aggregation Network for Self-supervised Depth-Pose Learning in Dynamic Scenes.
Proceedings of the 4th Conference on Robot Learning, 2020
A 112-765 GOPS/W FPGA-based CNN Accelerator using Importance Map Guided Adaptive Activation Sparsification for Pix2pix Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
ACM Trans. Reconfigurable Technol. Syst., 2019
A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes.
ACM Trans. Embed. Comput. Syst., 2019
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
An Auto Loss Co Jian Zhaompensation System for Capacitive-Coupled Body Channel Communication.
IEEE Trans. Biomed. Circuits Syst., 2019
Dynamic Channel Modeling and OFDM System Analysis for Capacitive Coupling Body Channel Communication.
IEEE Trans. Biomed. Circuits Syst., 2019
Sensors, 2019
A single clock cycle approximate adder with hybrid prediction and error compensation methods.
Microelectron. J., 2019
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
IEEE J. Solid State Circuits, 2019
A global and updatable ECG beat classification system based on recurrent neural networks and active learning.
Inf. Sci., 2019
IEEE Des. Test, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm<sup>2</sup>and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019
Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
Proceedings of the International Conference on Computer-Aided Design, 2019
Concrete: A Per-layer Configurable Framework for Evaluating DNN with Approximate Operators.
Proceedings of the IEEE International Conference on Acoustics, 2019
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Reconfigurable Technol. Syst., 2018
Bidirectional Database Storage and SQL Query Exploiting RRAM-Based Process-in-Memory Structure.
ACM Trans. Storage, 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A Five-Tissue-Layer Human Body Communication Circuit Model Tunable to Individual Characteristics.
IEEE Trans. Biomed. Circuits Syst., 2018
All-in-focus with directional-max-gradient flow and labeled iterative depth propagation.
Pattern Recognit., 2018
High linearity source-follower buffer based analog memory for analog convolutional neural network.
Microelectron. J., 2018
Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL.
Int. J. Reconfigurable Comput., 2018
Redundancy-bandwidth scalable techniques for signal-independent element transition rates in high-speed current-steering DACs.
Int. J. Circuit Theory Appl., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Interactive Hand Pose Estimation: Boosting accuracy in localizing extended finger joints.
Proceedings of the Visual Information Processing and Communication IX, Burlingame, CA, USA, 28 January 2018, 2018
Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
An extensible system simulator for intermittently-powered multiple-peripheral IoT devices.
Proceedings of the 6th International Workshop on Energy Harvesting & Energy-Neutral Sensing Systems, 2018
Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Energy Efficient ApproxSIFT Implementation for Image Mosaic with Approximate Computing Technologies.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
An Auto Loss Compensation System for Non-contact Capacitive Coupled Body Channel Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Bidirectional Recurrent Neural Network And Convolutional Neural Network (BiRCNN) For ECG Beat Classification.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Real-Time ECG Delineation with Randomly Selected Wavelet Transform Feature and Random Walk Estimation.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Region Aggregation Network: Improving Convolutional Neural Network for ECG Characteristic Detection.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Spatial-Temporal Attention Res-TCN for Skeleton-Based Dynamic Hand Gesture Recognition.
Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors.
Proceedings of the 55th Annual Design Automation Conference, 2018
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
Proceedings of the 55th Annual Design Automation Conference, 2018
Bi-stream Region Ensemble Network: Promoting Accuracy in Fingertip Localization from Stereo Images.
Proceedings of the British Machine Vision Conference 2018, 2018
An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
CMOS Image Sensor Data-Readout Method for Convolutional Operations with Processing Near Sensor Architecture.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
An Investigation on Ground Electrodes of Capacitive Coupling Human Body Communication.
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE Micro, 2017
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
IEEE J. Solid State Circuits, 2017
A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
IEEE J. Solid State Circuits, 2017
J. Circuits Syst. Comput., 2017
Two-stream binocular network: Accurate near field finger detection based on binocular images.
Proceedings of the 2017 IEEE Visual Communications and Image Processing, 2017
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
From "MISSION: IMPOSSIBLE" to mission possible: Fully flexible intelligent contact lens for image classification with analog-to-information processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017
Proceedings of the Image and Graphics - 9th International Conference, 2017
CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
A miniaturized wearable wireless hand gesture recognition system employing deep-forest classifier.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Using human body as a monopole antenna for energy harvesting from ambient electromagnetic energy.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Live demonstration: A hand gesture recognition wristband employing low power body channel communication.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications.
ACM Trans. Design Autom. Electr. Syst., 2016
A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Host cancelation-based spread spectrum watermarking for audio anti-piracy over Internet.
Secur. Commun. Networks, 2016
J. Comput. Sci. Technol., 2016
Spread spectrum audio watermarking based on perceptual characteristic aware extraction.
IET Signal Process., 2016
A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing.
IEICE Electron. Express, 2016
IEEE Des. Test, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016
A precision-improved processing architecture of physical computing for energy-efficient SIFT feature extraction.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
From model to FPGA: Software-hardware co-design for efficient neural network acceleration.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Switched by input: power efficient structure for RRAM-based convolutional neural network.
Proceedings of the 53rd Annual Design Automation Conference, 2016
HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016
CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling.
IEEE Trans. Parallel Distributed Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the International Conference on Wireless Communications & Signal Processing, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
A general scheme for noise-tolerant logic design based on probabilistic and DCVS approaches.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Blind drift calibration of sensor networks using signal space projection and Kalman filter.
Proceedings of the Tenth IEEE International Conference on Intelligent Sensors, 2015
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Physical computing circuit with no clock to establish Gaussian pyramid of SIFT algorithm.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Conference on Multimedia Big Data, BigMM 2015, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region.
ACM Trans. Embed. Comput. Syst., 2014
A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Multim. Tools Appl., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Int. J. Circuit Theory Appl., 2014
IEEE Des. Test, 2014
Low-complexity video encoder for smart eyes based on underdetermined blind signal separation.
CoRR, 2014
Physical Computing With No Clock to Implement the Gaussian Pyramid of SIFT Algorithm.
CoRR, 2014
A high-efficiency dual-channel photovoltaic power system for nonvolatile sensor nodes.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Design of multi-stage latency adders using detection and sequence-dependence between successive calculations.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the Fourth International Conference on Digital Information and Communication Technology and its Applicationsm DICTAP 2014, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Training itself: Mixed-signal training acceleration for memristor-based neural network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.
IEEE Trans. Parallel Distributed Syst., 2013
A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Speech Audio Process., 2013
A norm-space, adaptive, and blind audio watermarking algorithm by discrete wavelet transform.
Signal Process., 2013
Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture.
J. Comput., 2013
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits Devices Syst., 2013
IEICE Electron. Express, 2013
Increasing Compression Ratio of Low Complexity Compressive Sensing Video Encoder with Application-Aware Configurable Mechanism.
CoRR, 2013
A Novel Reconfigurable Computing Architecture for Image Signal Processing Using Circuit-Switched NoC and Synchronous Dataflow Model.
CoRR, 2013
Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation.
Proceedings of the 3rd Workshop on Irregular Applications - Architectures and Algorithms, 2013
Design of variable latency adder based on present and transitional states prediction.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the Multimedia and Ubiquitous Engineering, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013
Accelerating subsequence similarity search based on dynamic time warping distance with FPGA.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors.
Proceedings of the Design, Automation and Test in Europe, 2013
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine.
Multim. Tools Appl., 2012
A "Near-the-Best" System-Level Design Methodology of Multi-Core H.264 Video Decoder Based on the Parallelized Multi-Core Simulator.
J. Circuits Syst. Comput., 2012
Selective Host-Interference Cancellation: A New Informed Embedding Strategy for Spread Spectrum Watermarking.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Lifetime-Aware Battery Allocation for Wireless Sensor Network under Cost Constraints.
IEICE Trans. Commun., 2012
IEICE Trans. Electron., 2012
CoRR, 2012
A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2012
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
An energy harvesting nonvolatile sensor node and its application to distributed moving object detection.
Proceedings of the 11th International Conference on Information Processing in Sensor Networks (co-located with CPS Week 2012), 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
An informed unipolar spread spectrum modulation for self-synchronized robust watermarking.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the Sixth ACM International Conference on Distributed Event-Based Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Application specific sensor node architecture optimization - Experiences from field deployments.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Secur. Comput., 2011
An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Signal Process., 2011
Efficient construction of irregular codes with midterm block length and near-shannon performance.
IET Commun., 2011
IEICE Trans. Electron., 2011
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression.
IEICE Trans. Electron., 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 10th International Symposium on Autonomous Decentralized Systems, 2011
System-Level Evaluation of Video Processing System Using SimpleScalar-Based Multi-core Processor Simulator.
Proceedings of the 10th International Symposium on Autonomous Decentralized Systems, 2011
Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Sensors, 2010
IET Comput. Digit. Tech., 2010
Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting.
IET Circuits Devices Syst., 2010
IEICE Trans. Electron., 2010
IEICE Trans. Commun., 2010
A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator.
IEICE Electron. Express, 2010
Transmission Line Inspires A New Distributed Algorithm to Solve the Nonlinear Dynamical System of Physical Circuit
CoRR, 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
2009
Leakage Power Reduction through Dual V<sub>th</sub> Assignment Considering Threshold voltage Variation.
J. Circuits Syst. Comput., 2009
IEICE Trans. Electron., 2009
IEICE Electron. Express, 2009
Waveform Transmission Method, a New Waveform-relaxation Based Algorithm to Solve Ordinary Differential Equations in Parallel
CoRR, 2009
From devil to angel, transmission lines boost parallel computing of linear resistor networks
CoRR, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Battery allocation for wireless sensor network lifetime maximization under cost constraints.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Energy efficient architecture of sensor network node based on compression accelerator.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 2009 International Conference on Compilers, 2009
2008
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.
Sci. China Ser. F Inf. Sci., 2008
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008
Directed transmission method, a fully asynchronous approach to solve sparse linear systems in parallel.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008
Virtual Transmission Method, A New Distributed Algorithm to Solve Sparse Linear Systems.
Proceedings of the NCM 2008, The Fourth International Conference on Networked Computing and Advanced Information Management, Gyeongju, Korea, September 2-4, 2008, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
J. Circuits Syst. Comput., 2007
Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations.
Sci. China Ser. F Inf. Sci., 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation.
Proceedings of the Third International Conference on Natural Computation, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Consumer Electron., 2006
J. Circuits Syst. Comput., 2006
A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.
Proceedings of the Advances in Natural Computation, Second International Conference, 2006
A Noise-resilient Channel Estimation Algorithm Based on Two-Dimensional Hadamard Transform for OFDM Systems.
Proceedings of the Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 2006
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Improved Multiuser Detection for Fast FH/MFSK Systems.
Proceedings of the 2005 International Conference on Wireless Networks, 2005
A Robust and Low Complexity Coarse Frequency Offset Estimation Algorithm for DAB Receivers.
Proceedings of the 2005 International Conference on Wireless Networks, 2005
Proceedings of the Advances in Natural Computation, First International Conference, 2005
Proceedings of the Networking and Mobile Computing, Third International Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
Laplacian spectrum analysis and spanning tree algorithm for circuit partitioning problems.
Sci. China Ser. F Inf. Sci., 2003
2002
An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits.
Sci. China Ser. F Inf. Sci., 2002
2001
Sci. China Ser. F Inf. Sci., 2001
1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999