Krishnan Srinivasan

Orcid: 0000-0002-0692-1332

According to our database1, Krishnan Srinivasan authored at least 30 papers between 2004 and 2022.

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Bibliography

2022
Learning latent actions to control assistive robots.
Auton. Robots, 2022

2021
Recovery RL: Safe Reinforcement Learning With Learned Recovery Zones.
IEEE Robotics Autom. Lett., 2021

A Robot Cluster for Reproducible Research in Dexterous Manipulation.
CoRR, 2021

Dexterous Manipulation Primitives for the Real Robot Challenge.
CoRR, 2021


2020
Making Sense of Vision and Touch: Learning Multimodal Representations for Contact-Rich Tasks.
IEEE Trans. Robotics, 2020

Using a Variable-Friction Robot Hand to Determine Proprioceptive Features for Object Classification During Within-Hand-Manipulation.
IEEE Trans. Haptics, 2020

Learning to be Safe: Deep RL with a Safety Critic.
CoRR, 2020

Controlling Assistive Robots with Learned Latent Actions.
Proceedings of the 2020 IEEE International Conference on Robotics and Automation, 2020

Learning Hierarchical Control for Robust In-Hand Manipulation.
Proceedings of the 2020 IEEE International Conference on Robotics and Automation, 2020

2019
Making Sense of Vision and Touch: Self-Supervised Learning of Multimodal Representations for Contact-Rich Tasks.
Proceedings of the International Conference on Robotics and Automation, 2019

2018
Learning Modes of Within-Hand Manipulation.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

2017
Graph-based Neural Multi-Document Summarization.
Proceedings of the 21st Conference on Computational Natural Language Learning (CoNLL 2017), 2017

2011
Sampling-based garbage collection metadata management scheme for flash-based storage.
Proceedings of the IEEE 27th Symposium on Mass Storage Systems and Technologies, 2011

2009
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
ILP and heuristic techniques for system-level design on network processor architectures.
ACM Trans. Design Autom. Electr. Syst., 2007

Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints.
Integr., 2007

Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Linear-programming-based techniques for synthesis of network-on-chip architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A low complexity heuristic for design of custom network-on-chip architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Layout aware design of mesh based NoC architectures.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A technique for low energy mapping and routing in network-on-chip architectures.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

An automated technique for topology and route generation of application specific on-chip interconnection networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

SAGA: synthesis technique for guaranteed throughput NoC architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004


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