Yu Wang

According to our database1, Yu Wang authored at least 211 papers between 2006 and 2019.

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Bibliography

2019
[DL] A Survey of FPGA-based Neural Network Inference Accelerators.
TRETS, 2019

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Fine-Grained Sparse Accelerator for Multi-Precision DNN.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Compressed CNN Training with FPGA-based Accelerator.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA.
TRETS, 2018

Bidirectional Database Storage and SQL Query Exploiting RRAM-Based Process-in-Memory Structure.
TOS, 2018

Towards Real-Time Object Detection on Embedded Systems.
IEEE Trans. Emerging Topics Comput., 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Optimizing Cache Bypassing and Warp Scheduling for GPUs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Stuck-at Fault Tolerance in RRAM Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Nonparametric Topic Modeling with Neural Inference.
CoRR, 2018

Hu-Fu: Hardware and Software Collaborative Attack Framework against Neural Networks.
CoRR, 2018

Low power driven loop tiling for RRAM crossbar-based CNN.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

GraphIA: an in-situ accelerator for large-scale graph processing.
Proceedings of the International Symposium on Memory Systems, 2018

Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

RRAM Based Buffer Design for Energy Efficient CNN Accelerator.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training.
Proceedings of the 6th International Conference on Learning Representations, 2018

An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method.
Proceedings of the International Conference on Computer-Aided Design, 2018

NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Real-time object detection towards high power efficiency.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Rescuing memristor-based computing with non-linear resistance levels.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Training low bitwidth convolutional neural network on RRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes.
IEEE Trans. on Circuits and Systems, 2017

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Software-Hardware Codesign for Efficient Neural Network Acceleration.
IEEE Micro, 2017

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
J. Solid-State Circuits, 2017

Clutter suppression and GMTI for hypersonic vehicle borne SAR system with MIMO antenna.
IET Signal Processing, 2017

A Survey of FPGA Based Neural Network Accelerator.
CoRR, 2017

Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training.
CoRR, 2017

A Deep Learning Approach for Blind Drift Calibration of Sensor Networks.
CoRR, 2017

Energy-efficient SQL query exploiting RRAM-based process-in-memory structure.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Low-overhead implementation of logic encryption using gate replacement techniques.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Streaming sorting network based BWT acceleration on FPGA for lossless compression.
Proceedings of the International Conference on Field Programmable Technology, 2017

Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Exploring the Granularity of Sparsity in Convolutional Neural Networks.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017

Binary convolutional neural network on RRAM.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Computation-oriented fault-tolerance schemes for RRAM computing systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Guest Editorial: Design and Applications of Neuromorphic Computing System.
IEEE Trans. Multi-Scale Computing Systems, 2016

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. on Circuits and Systems, 2016

A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution.
IEEE Trans. on Circuits and Systems, 2016

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits and Systems, 2016

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol., 2016

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing.
IEEE Design & Test, 2016

ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA.
CoRR, 2016

Global and regional cortical connectivity maturation index (CCMI) of developmental human brain with quantification of short-range association tracts.
Proceedings of the Medical Imaging 2016: Biomedical Applications in Molecular, Structural, and Functional Imaging, San Diego, California, United States, 27 February, 2016

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Low power Convolutional Neural Networks on a chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Heterogeneous systems with reconfigurable neuromorphic computing accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

NXgraph: An efficient graph processing system on a single machine.
Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016

From model to FPGA: Software-hardware co-design for efficient neural network acceleration.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Approximate Frequent Itemset Mining for streaming data on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sparsity-oriented sparse solver design for circuit simulation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Switched by input: power efficient structure for RRAM-based convolutional neural network.
Proceedings of the 53rd Annual Design Automation Conference, 2016

RRAM based learning acceleration.
Proceedings of the 2016 International Conference on Compilers, 2016

Performance-centric register file design for GPUs using racetrack memory.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
HS3-DPG: Hierarchical Simulation for 3-D P/G Network.
IEEE Trans. VLSI Syst., 2015

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.
IEEE Trans. VLSI Syst., 2015

GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling.
IEEE Trans. Parallel Distrib. Syst., 2015

Real-Time High-Quality Stereo Vision System in FPGA.
IEEE Trans. Circuits Syst. Video Techn., 2015

RRAM-Based Analog Approximate Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

NXgraph: An Efficient Graph Processing System on a Single Machine.
CoRR, 2015

FASTrust: Feature analysis for third-party IP trust verification.
Proceedings of the 2015 IEEE International Test Conference, 2015

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hi-fi playback: tolerating position errors in shift operations of racetrack memory.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Rebooting Computing and Low-Power Image Recognition Challenge.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Coordinated static and dynamic cache bypassing for GPUs.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A self-aware data compression system on FPGA in Hadoop.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

An FPGA-based real-time simultaneous localization and mapping system.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

FPGA Acceleration of Recurrent Neural Network Based Language Model.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Spiking neural network with RRAM: can we use it for real-world application?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A fast parallel sparse solver for SPICE-based circuit simulators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A STT-RAM-based low-power hybrid register file for GPGPUs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

An accurate and low-cost PM2.5 estimation method based on Artificial Neural Network.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Modeling and optimization of low power resonant clock mesh.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region.
ACM Trans. Embedded Comput. Syst., 2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.
JETC, 2014

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.
IEEE Design & Test, 2014

Network flow-based simultaneous retiming and slack budgeting for low power design.
CoRR, 2014

Efficient region-aware P/G TSV planning for 3D ICs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Energy efficient spiking neural network design with RRAM devices.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Large scale recurrent neural network on GPU.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

A universal FPGA-based floating-point matrix processor for mobile systems.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Online scheduling for FPGA computation in the Cloud.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Accelerating frequent item counting with FPGA.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

ICE: Inline calibration for memristor crossbar-based computing engine.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient neural networks for big data analytics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Enabling FPGAs in the cloud.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Training itself: Mixed-signal training acceleration for memristor-based neural network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Statistical analysis of random telegraph noise in digital circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.
IEEE Trans. Parallel Distrib. Syst., 2013

NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.
Journal of Circuits, Systems, and Computers, 2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits, Devices & Systems, 2013

Assessment of Circuit Optimization Techniques Under NBTI.
IEEE Design & Test, 2013

Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation.
Proceedings of the 3rd Workshop on Irregular Applications - Architectures and Algorithms, 2013

RALP: Reconvergence-aware layer partitioning for 3D FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Whitespace-aware TSV arrangement in 3D clock tree synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

TSV-aware topology generation for 3D Clock Tree Synthesis.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Memristor-based approximated computation.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Real-time high-quality stereo vision system in FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Accelerating subsequence similarity search based on dynamic time warping distance with FPGA.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

HS3DPG: Hierarchical simulation for 3D P/G network.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. VLSI Syst., 2012

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing.
J. Electrical and Computer Engineering, 2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Improving energy efficiency of write-asymmetric memories by log style write.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Probabilistic Brain Fiber Tractography on GPUs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Parallel Circuit Simulation on Multi/Many-core Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

FPGA based memory efficient high resolution stereo vision system for video tolling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Pub/Sub on stream: a multi-core based message broker with QoS support.
Proceedings of the Sixth ACM International Conference on Distributed Event-Based Systems, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Sparse LU factorization for parallel circuit simulation on GPU.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

An adaptive LU factorization algorithm for parallel circuit simulation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Power Gating Aware Task Scheduling in MPSoC.
IEEE Trans. VLSI Syst., 2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.
IEEE Trans. VLSI Syst., 2011

An FPGA-based accelerator for LambdaRank in Web search engines.
TRETS, 2011

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Sec. Comput., 2011

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. on Circuits and Systems, 2011

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.
IEICE Transactions, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Circuit-level delay modeling considering both TDDB and NBTI.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Gemma in April: A matrix-like parallel programming architecture on OpenCL.
Proceedings of the Design, Automation and Test in Europe, 2011

Tree-Based Partitioning Approach for Network-on-Chip Synthesis.
Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

On-chip hybrid power supply system for wireless sensor nodes.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Output remapping technique for critical paths soft-error rate reduction.
IET Computers & Digital Techniques, 2010

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting.
IET Circuits, Devices & Systems, 2010

FPGA and GPU implementation of large scale SpMV.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Efficient PageRank and SpMV Computation on AMD GPUs.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

LambdaRank acceleration for relevance ranking in web search engines (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FPMR: MapReduce framework on FPGA.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Simultaneous slack budgeting and retiming for synchronous circuits optimization.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation.
Journal of Circuits, Systems, and Computers, 2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
International Journal of Parallel Programming, 2009

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.
IEICE Transactions, 2009

Temperature-Aware NBTI Modeling Techniques in Digital Circuits.
IEICE Transactions, 2009

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Modern Floorplanning with Boundary Clustering Constraint.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

NBTI-aware statistical circuit delay assessment.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

RankBoost Acceleration on both NVIDIA CUDA and ATI Stream Platforms.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

Multi-objective Floorplanning Based on Fuzzy Logic.
Proceedings of the Sixth International Conference on Fuzzy Systems and Knowledge Discovery, 2009

FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Gate replacement techniques for simultaneous leakage and aging optimization.
Proceedings of the Design, Automation and Test in Europe, 2009

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A case study of on-chip sensor network in multiprocessor system-on-chip.
Proceedings of the 2009 International Conference on Compilers, 2009

A framework for estimating NBTI degradation of microarchitectural components.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. VLSI Syst., 2008

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Dynamic TDM virtual circuit implementation for NoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Modeling of PMOS NBTI Effect Considering Temperature Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A power gating scheme for ground bounce reduction during mode transition.
Proceedings of the 25th International Conference on Computer Design, 2007

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction.
Journal of Circuits, Systems, and Computers, 2006

IR-drop Reduction Through Combinational Circuit Partitioning.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.
Proceedings of the Advances in Natural Computation, Second International Conference, 2006

Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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