Yuan Xie

According to our database1, Yuan Xie authored at least 355 papers between 2000 and 2018.

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Bibliography

2018
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications.
IEEE Trans. VLSI Syst., 2018

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.
IEEE Trans. VLSI Syst., 2018

Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation.
IEEE Trans. VLSI Syst., 2018

Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes.
IEEE Trans. VLSI Syst., 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.
IEEE Micro, 2018

Die Stacking Is Happening.
IEEE Micro, 2018

Stuck-at Fault Tolerance in RRAM Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

In-memory multiplication engine with SOT-MRAM based stochastic computing.
CoRR, 2018

Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training.
CoRR, 2018

Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler.
CoRR, 2018

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads.
Computer Architecture Letters, 2018

Crossbar-Aware Neural Network Pruning.
IEEE Access, 2018

AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

RADAR: a 3D-reRAM based DNA alignment accelerator architecture.
Proceedings of the 55th Annual Design Automation Conference, 2018

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Thermomechanical Stress-Aware Management for 3-D IC Designs.
IEEE Trans. VLSI Syst., 2017

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.
ACM Trans. Embedded Comput. Syst., 2017

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Software-Hardware Codesign for Efficient Neural Network Acceleration.
IEEE Micro, 2017

Overview of 3-D Architecture Design Opportunities and Techniques.
IEEE Design & Test, 2017

Incidental computing on IoT nonvolatile processors.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

DRISA: a DRAM-based reconfigurable in-situ accelerator.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Cost-effective design of scalable high-performance systems using active and passive interposers.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Building energy-efficient multi-level cell STT-RAM caches with data compression.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Computation-oriented fault-tolerance schemes for RRAM computing systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.
IEEE Trans. VLSI Syst., 2016

TSocket: Thermal Sustainable Power Budgeting.
ACM Trans. Design Autom. Electr. Syst., 2016

Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016

BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.
J. Comput. Sci. Technol., 2016

CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis.
CoRR, 2016

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
CoRR, 2016

Redesigning software and systems for non-volatile processors on self-powered devices.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Thermal-aware 3D design for side-channel information leakage.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Scalable memory fabric for silicon interposer-based multi-core systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016

NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Neural network transformation under hardware constraints.
Proceedings of the 2016 International Conference on Compilers, 2016

Architecture design with STT-RAM: Opportunities and challenges.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Die-stacking Architecture
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2015

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.
IEEE Trans. VLSI Syst., 2015

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst., 2015

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.
ACM Trans. Design Autom. Electr. Syst., 2015

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.
ACM Trans. Design Autom. Electr. Syst., 2015

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi-Scale Computing Systems, 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.
TACO, 2015

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
TACO, 2015

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.
IEEE Micro, 2015

A Write-Aware STTRAM-Based Register File Architecture for GPGPU.
JETC, 2015

Memory and Storage System Design with Nonvolatile Memory Technologies.
IPSJ Trans. System LSI Design Methodology, 2015

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems.
Computer Architecture Letters, 2015

Leveraging nonvolatility for architecture design with emerging NVM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Architecture exploration for ambient energy harvesting nonvolatile processors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-powered wearable sensor node: Challenges and opportunities.
Proceedings of the 2015 International Conference on Compilers, 2015

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond.
ACM Trans. Design Autom. Electr. Syst., 2014

Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Endurance-aware cache line management for non-volatile caches.
TACO, 2014

Building and Optimizing MRAM-Based Commodity Memories.
TACO, 2014

Preventing STT-RAM Last-Level Caches from Port Obstruction.
TACO, 2014

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology.
JETC, 2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.
JETC, 2014

An Embedded Co-AdaBoost based construction of software document relation coupled resource spaces for cyber-physical society.
Future Generation Comp. Syst., 2014

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.
IEEE Design & Test, 2014

Compact models and model standard for 2.5D and 3D integration.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Efficient region-aware P/G TSV planning for 3D ICs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Enabling high-performance LPDDRx-compatible MRAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Making B+-tree efficient in PCM-based main memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

ProactiveDRAM: A DRAM-initiated retention management scheme.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Architecting 3D vertical resistive memory for next-generation storage systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

TSV power supply array electromigration lifetime analysis in 3D ICS.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Reliability-aware cross-point resistive memory design.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Thermal-Sustainable Power Budgeting for Dynamic Threading.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface.
TACO, 2013

WADE: Writeback-aware dynamic cache management for NVM-based main memory system.
TACO, 2013

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.
TACO, 2013

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.
JETC, 2013

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.
JETC, 2013

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.
Integration, 2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits, Devices & Systems, 2013

Assessment of Circuit Optimization Techniques Under NBTI.
IEEE Design & Test, 2013

Kiln: closing the performance gap between systems with and without persistence support.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Cost-driven 3D design optimization with metal layer reduction technique.
Proceedings of the International Symposium on Quality Electronic Design, 2013

CPDI: Cross-power-domain interface circuit design in monolithic 3D technology.
Proceedings of the International Symposium on Quality Electronic Design, 2013

TSV-aware topology generation for 3D Clock Tree Synthesis.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Designing scratchpad memory architecture with emerging STT-RAM memory technologies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Low power multi-level-cell resistive memory design with incomplete data mapping.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Thermomechanical stress-aware management for 3D IC designs.
Proceedings of the Design, Automation and Test in Europe, 2013

Future memory and interconnect technologies.
Proceedings of the Design, Automation and Test in Europe, 2013

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches.
Proceedings of the Design, Automation and Test in Europe, 2013

Designing energy-efficient NoC for real-time embedded systems through slack optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Understanding the trade-offs in multi-level cell ReRAM memory design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Low-Power Design of Emerging Memory Technologies.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.
IEEE Trans. VLSI Syst., 2012

Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs.
ACM Trans. Design Autom. Electr. Syst., 2012

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.
ACM Trans. Embedded Comput. Syst., 2012

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing.
J. Electrical and Computer Engineering, 2012

ESL Design Methodology.
J. Electrical and Computer Engineering, 2012

An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation.
Proceedings of the Eighth International Conference on Semantics, Knowledge and Grids, 2012

MAGE: adaptive granularity and ECC for resilient and power efficient memory systems.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Energy-efficient GPU design with reconfigurable in-package graphics memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Design trade-offs for high density cross-point resistive memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mitigating electromigration of power supply networks using bidirectional current stress.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Modeling and design exploration of FBDRAM as on-chip memory.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Point and discard: a hard-error-tolerant architecture for non-volatile last level caches.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Low power memristor-based ReRAM design with Error Correcting Code.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.
IEEE Trans. VLSI Syst., 2011

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model.
IEEE Trans. Dependable Sec. Comput., 2011

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Sec. Comput., 2011

Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.
TACO, 2011

Editorial- three-dimensional integrated circuits design.
IET Computers & Digital Techniques, 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Computers & Digital Techniques, 2011

Three-dimensional Integrated Circuits: Design, EDA, and Architecture.
Foundations and Trends in Electronic Design Automation, 2011

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Modeling, Architecture, and Applications for Emerging Memory Technologies.
IEEE Design & Test of Computers, 2011

Impact of Circuit Degradation on FPGA Design Security.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Moguls: a model to explore the memory hierarchy for bandwidth improvements.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

F2BFLY: an on-chip free-space optical network with wavelength-switching.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Energy-efficient multi-level cell phase-change memory system with data encoding.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Bandwidth-aware reconfigurable cache design with hybrid memory technologies.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Enabling architectural innovations using non-volatile memory.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

An energy-efficient 3D CMP design with fine-grained voltage scaling.
Proceedings of the Design, Automation and Test in Europe, 2011

Design implications of memristor-based RRAM cross-point structures.
Proceedings of the Design, Automation and Test in Europe, 2011

Automated mapping for reconfigurable single-electron transistor arrays.
Proceedings of the 48th Design Automation Conference, 2011

System-level design space exploration for three-dimensional (3D) SoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A frequent-value based PRAM memory architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Enabling quality-of-service in nanophotonic network-on-chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

On-chip hybrid power supply system for wireless sensor nodes.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Total Power Optimization for Combinational Logic Using Genetic Algorithms.
Signal Processing Systems, 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. VLSI Syst., 2010

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Design exploration of hybrid caches with disparate memory technologies.
TACO, 2010

Test-access mechanism optimization for core-based three-dimensional SOCs.
Microelectronics Journal, 2010

3D Stacked Microprocessor: Are We There Yet?
IEEE Micro, 2010

Processor Architecture Design Using 3D Integration Technology.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.
Proceedings of the Conference on High Performance Computing Networking, 2010

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Modeling TSV open defects in 3D-stacked DRAM.
Proceedings of the 2011 IEEE International Test Conference, 2010

Low-power dual-element memristor based memory design.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Energy- and endurance-aware design of phase change memory caches.
Proceedings of the Design, Automation and Test in Europe, 2010

Cost-aware three-dimensional (3D) many-core multiprocessor design.
Proceedings of the 47th Design Automation Conference, 2010

Cost-driven 3D integration with interconnect layers.
Proceedings of the 47th Design Automation Conference, 2010

Impact of process variations on emerging memristor.
Proceedings of the 47th Design Automation Conference, 2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Energy and performance driven circuit design for emerging phase-change memory.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Architectural benefits and design challenges for three-dimensional integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

3D memory stacking for fast checkpointing/restore applications.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.
IEEE Trans. Dependable Sec. Comput., 2009

Process-Variation-Aware Adaptive Cache Architecture and Management.
IEEE Trans. Computers, 2009

Scan-chain design and optimization for three-dimensional integrated circuits.
JETC, 2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
International Journal of Parallel Programming, 2009

Temperature-Aware NBTI Modeling Techniques in Digital Circuits.
IEICE Transactions, 2009

Statistical High-Level Synthesis under Process Variability.
IEEE Design & Test of Computers, 2009

Guest Editors' Introduction: Opportunities and Challenges of 3D Integration.
IEEE Design & Test of Computers, 2009

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

NBTI-aware statistical circuit delay assessment.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Emerging technologies and their impact on system design.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Hybrid cache architecture with disparate memory technologies.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.
Proceedings of the 27th International Conference on Computer Design, 2009

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.
Proceedings of the 27th International Conference on Computer Design, 2009

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Power and performance of read-write aware Hybrid Caches with non-volatile memories.
Proceedings of the Design, Automation and Test in Europe, 2009

Gate replacement techniques for simultaneous leakage and aging optimization.
Proceedings of the Design, Automation and Test in Europe, 2009

CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.
Proceedings of the 2009 International Conference on Compilers, 2009

Variation-aware resource sharing and binding in behavioral synthesis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A criticality-driven microarchitectural three dimensional (3D) floorplanner.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A framework for estimating NBTI degradation of microarchitectural components.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Tolerating process variations in high-level synthesis using transparent latches.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Arithmetic unit design using 180nm TSV-based 3D stacking technology.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Case Study of Reliability-Aware and Low-Power Design.
IEEE Trans. VLSI Syst., 2008

Design Space Exploration for 3-D Cache.
IEEE Trans. VLSI Syst., 2008

Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Sec. Comput., 2008

Editorial: Special issue on 3D integrated circuits and microarchitectures.
JETC, 2008

Power optimization for FinFET-based circuits using genetic algorithms.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

ILP-based scheme for timing variation-aware scheduling and resource binding.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Two-dimensional crosstalk avoidance codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Test-Access Solutions for Three-Dimensional SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Hierarchical Soft Error Estimation Tool (HSEET).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Test-access mechanism optimization for core-based three-dimensional SOCs.
Proceedings of the 26th International Conference on Computer Design, 2008

Comparative analysis of NBTI effects on low power and high performance flip-flops.
Proceedings of the 26th International Conference on Computer Design, 2008

Thermal-aware reliability analysis for platform FPGAs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A low-power phase change memory based hybrid cache architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Technology, CAD tools, and designs for emerging 3D integration technology.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Variation Aware High Level Synthesis Framework.
Proceedings of the Design, Automation and Test in Europe, 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

Variability-driven module selection with joint design time optimization and post-silicon tuning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Reliability-aware Co-synthesis for Embedded Systems.
VLSI Signal Processing, 2007

Code Decompression Unit Design for VLIW Embedded Processors.
IEEE Trans. VLSI Syst., 2007

Code Compression for VLIW Embedded Systems Using a Self-Generating Table.
IEEE Trans. VLSI Syst., 2007

Processor Design in 3D Die-Stacking Technologies.
IEEE Micro, 2007

On-chip bus thermal analysis and optimisation.
IET Computers & Digital Techniques, 2007

Leakage-Aware Interconnect for On-Chip Network
CoRR, 2007

Reliability-Centric High-Level Synthesis
CoRR, 2007

Thermal-Aware Task Allocation and Scheduling for Embedded Systems
CoRR, 2007

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Architecting Microprocessor Components in 3D Design Space.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Collaborative VLSI-CAD Instruction in the Digital Sandbox.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Variation Impact on SER of Combinational Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variation Analysis of CAM Cells.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Modeling of PMOS NBTI Effect Considering Temperature Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Scan chain design for three-dimensional integrated circuits (3D ICs).
Proceedings of the 25th International Conference on Computer Design, 2007

FPGA routing architecture analysis under variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A novel criticality computation method in statistical timing analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.
VLSI Signal Processing, 2006

Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding.
IEEE Trans. VLSI Syst., 2006

Design space exploration for 3D architectures.
JETC, 2006

Reliability Concerns in Embedded System Designs.
IEEE Computer, 2006

A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Modeling the Impact of Process Variation on Critical Charge Distribution.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Reliability-Aware SOC Voltage Islands Partition and Floorplan.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Dependability Analysis of Nano-scale FinFET circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Delay and Energy Efficient Data Transmission for On-Chip Buses.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Guaranteeing performance yield in high-level synthesis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

On-chip bus thermal analysis and optimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

FLAW: FPGA lifetime awareness.
Proceedings of the 43rd Design Automation Conference, 2006

Optimal topology exploration for application-specific 3D architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Leakage Optimized DECAP Design for FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

An ILP Formulation for Reliability-Oriented High-Level Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reliability-Centric Hardware/Software Co-Design.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Thermal-Aware Floorplanning Using Genetic Algorithms.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Three-Dimensional Cache Design Exploration Using 3DCacti.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Temperature-Sensitive Loop Parallelization for Chip Multiprocessors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.
Proceedings of the 2005 Design, 2005

Leakage-Aware Interconnect for On-Chip Network.
Proceedings of the 2005 Design, 2005

Reliability-Centric High-Level Synthesis.
Proceedings of the 2005 Design, 2005

Thermal-Aware Task Allocation and Scheduling for Embedded Systems.
Proceedings of the 2005 Design, 2005

Low-leakage robust SRAM cell design for sub-100nm technologies.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Designing reliable circuit in the presence of soft errors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
The Effect of Threshold Voltages on the Soft Error Rate.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Improving soft-error tolerance of FPGA configuration bits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Design of a nanosensor array architecture.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

LZW-Based Code Compression for VLIW Embedded Systems.
Proceedings of the 2004 Design, 2004

Reliability-Aware Co-Synthesis for Embedded Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Augmenting Platform-Based Design with Synthesis Tools.
Journal of Circuits, Systems, and Computers, 2003

Effect of Power Optimizations on Soft Error Rate.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding.
Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003

Profile-Driven Selective Code Compression.
Proceedings of the 2003 Design, 2003

2002
Code Compression for VLIW Processors Using Variable-to-Fixed Coding.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
A code decompression architecture for VLIW processors.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Code Compression for VLIW Processors.
Proceedings of the Data Compression Conference, 2001

Allocation and scheduling of conditional task graph in hardware/software co-synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Co-synthesis with custom ASICs.
Proceedings of ASP-DAC 2000, 2000


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